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AgeCommit message (Expand)Author
2017-07-27Work in progress.Pavel V. Shatov (Meister)
2017-07-25Work in progress.Pavel V. Shatov (Meister)
2017-07-25Wide operand loader needs simplification...Pavel V. Shatov (Meister)
2017-07-25Trying to fix the bug during calculation of SN in systolic multiplier.Pavel V. Shatov (Meister)
2017-07-24Started adding top-level wrapper.Pavel V. Shatov (Meister)
2017-07-23Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ...Pavel V. Shatov (Meister)
2017-07-23Converted pe_t array into a FIFO too. No more nasty messages during synthesis...Pavel V. Shatov (Meister)
2017-07-20Force inference of distributed memory for the simple FIFO used to store carries.Pavel V. Shatov (Meister)
2017-07-20Converted pe_c_out_mem two-dimensional array into a FIFO.Pavel V. Shatov (Meister)
2017-07-19Fixed bug in systolic multiplier (swapped indices), it onlyPavel V. Shatov (Meister)
2017-07-19Added pre-multiplication step.Pavel V. Shatov (Meister)
2017-07-19Finished modular exponentiation module:Pavel V. Shatov (Meister)
2017-07-18Started adding exponentiator module w/ testbench.Pavel V. Shatov (Meister)
2017-07-13Systolic multiplier simplified a bit:Pavel V. Shatov (Meister)
2017-07-10 * made separate file for low-level settingsPavel V. Shatov (Meister)
2017-07-04Fixed generic/vendor low-level primitives switch.Pavel V. Shatov (Meister)
2017-07-04Fixing generic/vendor primitive switching...Pavel V. Shatov (Meister)
2017-07-01Started porting generic multiplier to Xilinx primitives.Pavel V. Shatov (Meister)
2017-07-01Added generic/vendor-specific primitive selector for simulation.Pavel V. Shatov (Meister)
2017-07-01Cleaned up Verilog sourcesPavel V. Shatov (Meister)
2017-07-01Added 512-bit test vectorPavel V. Shatov (Meister)
2017-07-01Finished modulus-dependent coefficient calculation module:Pavel V. Shatov (Meister)
2017-06-27Added Montgomery modulus-dependent coefficient calculation blockPavel V. Shatov (Meister)
2017-06-27Added Montgomery factor calculation blockPavel V. Shatov (Meister)
2017-06-27Added systolic modular multiplier w/ testbench.Pavel V. Shatov (Meister)
2017-06-27Added generic processing elements.Pavel V. Shatov (Meister)
2017-06-27Start conversion to systolic architecture.Pavel V. Shatov (Meister)
2016-06-14Initial commitPaul Selkirk