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Modular exponentiation using the Artix-7 FPGA
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2018-12-19
Use primitives from core/lib
HEAD
master
Pavel V. Shatov (Meister)
2017-08-12
Added STM32 code to test CRT mode in hardware.
Pavel V. Shatov (Meister)
2017-08-11
Work in progress.
Pavel V. Shatov (Meister)
2017-08-09
Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prev...
Pavel V. Shatov (Meister)
2017-08-07
* Added readme file
v0.20
Pavel V. Shatov (Meister)
2017-07-25
Trying to fix the bug during calculation of SN in systolic multiplier.
Pavel V. Shatov (Meister)
2017-07-23
Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ...
Pavel V. Shatov (Meister)
2017-07-10
* made separate file for low-level settings
Pavel V. Shatov (Meister)
2017-07-04
Fixed generic/vendor low-level primitives switch.
Pavel V. Shatov (Meister)
2017-07-04
Fixing generic/vendor primitive switching...
Pavel V. Shatov (Meister)
2017-07-01
Started porting generic multiplier to Xilinx primitives.
Pavel V. Shatov (Meister)
2017-07-01
Added generic/vendor-specific primitive selector for simulation.
Pavel V. Shatov (Meister)
2017-07-01
Finished modulus-dependent coefficient calculation module:
Pavel V. Shatov (Meister)
2017-06-27
Added generic processing elements.
Pavel V. Shatov (Meister)
