Age | Commit message (Collapse) | Author | |
---|---|---|---|
2017-07-23 | Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ↵ | Pavel V. Shatov (Meister) | |
just fine: 10% slices 8% block memory 33% DSPs | |||
2017-06-27 | Start conversion to systolic architecture. | Pavel V. Shatov (Meister) | |
2016-06-14 | Initial commit | Paul Selkirk | |