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Modular exponentiation using the Artix-7 FPGA
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modexpa7_systolic_multiplier.v
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2017-08-11
Minor cleanup.
Pavel V. Shatov (Meister)
2017-08-11
Work in progress.
Pavel V. Shatov (Meister)
2017-08-06
* Moved systolic processing element array into a separate module.
Pavel V. Shatov (Meister)
2017-07-27
Work in progress.
Pavel V. Shatov (Meister)
2017-07-25
Work in progress.
Pavel V. Shatov (Meister)
2017-07-25
Wide operand loader needs simplification...
Pavel V. Shatov (Meister)
2017-07-25
Trying to fix the bug during calculation of SN in systolic multiplier.
Pavel V. Shatov (Meister)
2017-07-23
Converted pe_t array into a FIFO too. No more nasty messages during synthesis...
Pavel V. Shatov (Meister)
2017-07-20
Converted pe_c_out_mem two-dimensional array into a FIFO.
Pavel V. Shatov (Meister)
2017-07-19
Fixed bug in systolic multiplier (swapped indices), it only
Pavel V. Shatov (Meister)
2017-07-13
Systolic multiplier simplified a bit:
Pavel V. Shatov (Meister)
2017-07-10
* made separate file for low-level settings
Pavel V. Shatov (Meister)
2017-07-04
Fixed generic/vendor low-level primitives switch.
Pavel V. Shatov (Meister)
2017-07-01
Started porting generic multiplier to Xilinx primitives.
Pavel V. Shatov (Meister)
2017-06-27
Added systolic modular multiplier w/ testbench.
Pavel V. Shatov (Meister)
