| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-08-11 | Minor cleanup. | Pavel V. Shatov (Meister) | |
| 2017-08-11 | CRT mode seems to work. Finally. | Pavel V. Shatov (Meister) | |
| Strangely enough non-CRT mode continues to work fine(!). One does not simply add a feature without breaking something else. Very suspicious... | |||
| 2017-08-11 | Work in progress. | Pavel V. Shatov (Meister) | |
| 2017-08-06 | * Moved systolic processing element array into a separate module. | Pavel V. Shatov (Meister) | |
| * Finished top-level wrapper module. | |||
| 2017-07-19 | Added pre-multiplication step. | Pavel V. Shatov (Meister) | |
| Added 512-bit testbench. | |||
| 2017-07-19 | Finished modular exponentiation module: | Pavel V. Shatov (Meister) | |
| * works in simulator * passes synthesis without major issues Started adding pre-multiplication logic... | |||
| 2017-07-18 | Started adding exponentiator module w/ testbench. | Pavel V. Shatov (Meister) | |
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index : core/math/modexpa7 | |
| Modular exponentiation using the Artix-7 FPGA | git repositories |
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