Age | Commit message (Expand) | Author |
---|---|---|
2017-07-01 | Started porting generic multiplier to Xilinx primitives. | Pavel V. Shatov (Meister) |
2017-07-01 | Added generic/vendor-specific primitive selector for simulation. | Pavel V. Shatov (Meister) |
2017-07-01 | Cleaned up Verilog sources | Pavel V. Shatov (Meister) |
2017-07-01 | Added 512-bit test vector | Pavel V. Shatov (Meister) |
2017-07-01 | Finished modulus-dependent coefficient calculation module: | Pavel V. Shatov (Meister) |
2017-06-27 | Added test vectors, use scripts from the C model to (re-)generate them. | Pavel V. Shatov (Meister) |
2017-06-27 | Added Montgomery modulus-dependent coefficient calculation block | Pavel V. Shatov (Meister) |
2017-06-27 | Added Montgomery factor calculation block | Pavel V. Shatov (Meister) |
2017-06-27 | Added systolic modular multiplier w/ testbench. | Pavel V. Shatov (Meister) |
2017-06-27 | Added generic processing elements. | Pavel V. Shatov (Meister) |
2017-06-27 | Start conversion to systolic architecture. | Pavel V. Shatov (Meister) |
2016-06-14 | Initial commit | Paul Selkirk |