diff options
Diffstat (limited to 'src/tb/tb_exponentiator.v')
| -rw-r--r-- | src/tb/tb_exponentiator.v | 139 |
1 files changed, 135 insertions, 4 deletions
diff --git a/src/tb/tb_exponentiator.v b/src/tb/tb_exponentiator.v index 16be0a5..440fedc 100644 --- a/src/tb/tb_exponentiator.v +++ b/src/tb/tb_exponentiator.v @@ -63,6 +63,8 @@ module tb_exponentiator; reg rst_n;
reg ena;
+ reg crt;
+
reg [ 3: 0] n_num_words;
reg [ 8: 0] d_num_bits;
@@ -170,6 +172,8 @@ module tb_exponentiator; .ena (ena),
.rdy (rdy),
+ .crt (crt),
+
.m_bram_addr (core_m_addr),
.d_bram_addr (core_d_addr),
.f_bram_addr (core_f_addr),
@@ -206,9 +210,14 @@ module tb_exponentiator; #200;
rst_n = 1'b1;
#100;
-
- test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
- test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);
+
+ // test "honest" exponentiation
+// test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
+// test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);
+
+ // test crt mode
+ test_exponent_192(M_384, DP_192, FACTOR_P_192, P_192, P_COEFF_192, MP_192);
+ //test_exponent_192(M_384, DQ_192, FACTOR_Q_192, Q_192, Q_COEFF_192, MQ_192);
end
@@ -216,7 +225,6 @@ module tb_exponentiator; //
// Test Tasks
//
-
task test_exponent_384;
// input [383:0] m;
@@ -234,6 +242,8 @@ module tb_exponentiator; n_num_words = 4'd11; // set number of words
d_num_bits = 9'd383; // set number of bits
//
+ crt = 0; // disable crt mode
+ //
write_memory_384(m, d, f, n, n_coeff); // fill memory
ena = 1; // start operation @@ -276,6 +286,8 @@ module tb_exponentiator; n_num_words = 4'd15; // set number of words
d_num_bits = 9'd511; // set number of bits
//
+ crt = 0; // disable crt mode
+ //
write_memory_512(m, d, f, n, n_coeff); // fill memory
ena = 1; // start operation @@ -301,6 +313,49 @@ module tb_exponentiator; //
endtask + task test_exponent_192;
+ // + input [383:0] m;
+ input [191:0] d;
+ input [191:0] f;
+ input [191:0] n;
+ input [191:0] n_coeff;
+ input [191:0] s;
+ reg [191:0] r;
+ //
+ integer i;
+ // + begin
+ //
+ n_num_words = 4'd5; // set number of words
+ d_num_bits = 9'd191; // set number of bits
+ //
+ crt = 1; // enable crt mode
+ //
+ write_memory_192(m, d, f, n, n_coeff); // fill memory
+ + ena = 1; // start operation + #10; //
+ ena = 0; // clear flag
+ + while (!rdy) #10; // wait for operation to complete
+ read_memory_192(r); // get result from memory +
+ $display(" calculated: %x", r); // display result
+ $display(" expected: %x", s); //
+
+ // check calculated value
+ if (r === s) begin + $display(" OK");
+ $display("SUCCESS: Test passed."); + end else begin
+ $display(" ERROR");
+ $display("FAILURE: Test not passed.");
+ end
+ //
+ end + //
+ endtask //
// write_memory_384
@@ -409,6 +464,59 @@ module tb_exponentiator; //
+ // write_memory_192
+ //
+ task write_memory_192;
+ //
+ input [383:0] m;
+ input [191:0] d;
+ input [191:0] f;
+ input [191:0] n;
+ input [191:0] n_coeff;
+ reg [383:0] m_shreg;
+ reg [191:0] f_shreg;
+ reg [191:0] d_shreg;
+ reg [191:0] n_shreg;
+ reg [191:0] n_coeff_shreg;
+ //
+ begin + //
+ tb_mdfn_wren = 1; // start filling memories + m_shreg = m; // preload shift register
+ d_shreg = d; // preload shift register
+ f_shreg = f; // preload shift register
+ n_shreg = n; // preload shift register
+ n_coeff_shreg = n_coeff; // preload shift register
+ // + for (w=0; w<NUM_WORDS_384; w=w+1) begin // write all words + tb_mdfn_addr = w[3:0]; // set address + tb_m_data = m_shreg[31:0]; // set data + tb_d_data = d_shreg[31:0]; // set data + tb_f_data = f_shreg[31:0]; // set data + tb_n_data = n_shreg[31:0]; // set data + tb_n_coeff_data = n_coeff_shreg[31:0]; // set data + m_shreg = {{32{1'bX}}, m_shreg[383:32]}; // update shift register + d_shreg = {{32{1'bX}}, d_shreg[191:32]}; // update shift register + f_shreg = {{32{1'bX}}, f_shreg[191:32]}; // update shift register + n_shreg = {{32{1'bX}}, n_shreg[191:32]}; // update shift register + n_coeff_shreg = {{32{1'bX}}, n_coeff_shreg[191:32]}; // update shift register + #10; // wait for 1 clock tick + end + // + tb_mdfn_addr = {4{1'bX}}; // wipe addresses + tb_m_data = {32{1'bX}}; // wipe data + tb_d_data = {32{1'bX}}; // wipe data + tb_f_data = {32{1'bX}}; // wipe data + tb_n_data = {32{1'bX}}; // wipe data + tb_n_coeff_data = {32{1'bX}}; // wipe data + tb_mdfn_wren = 0; // stop filling memory
+ //
+ end
+ //
+ endtask +
+
+ //
// read_memory_384
//
task read_memory_384;
@@ -455,6 +563,29 @@ module tb_exponentiator; //
endtask + //
+ // read_memory_192
+ //
+ task read_memory_192;
+ //
+ output [191:0] r;
+ reg [191:0] r_shreg;
+ //
+ begin
+ //
+ for (w=0; w<NUM_WORDS_384/2; w=w+1) begin // read result word-by-word + tb_r_addr = w[3:0]; // set address + #10; // wait for 1 clock tick + r_shreg = {tb_r_data, r_shreg[191:32]}; // store data word + end
+ //
+ tb_r_addr = {4{1'bX}}; // wipe address
+ r = r_shreg; // return
+ //
+ end
+ //
+ endtask +
endmodule
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