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Diffstat (limited to 'src/rtl/pe/modexpa7_pe_mul.v')
-rw-r--r--src/rtl/pe/modexpa7_pe_mul.v33
1 files changed, 19 insertions, 14 deletions
diff --git a/src/rtl/pe/modexpa7_pe_mul.v b/src/rtl/pe/modexpa7_pe_mul.v
index ff15981..6453049 100644
--- a/src/rtl/pe/modexpa7_pe_mul.v
+++ b/src/rtl/pe/modexpa7_pe_mul.v
@@ -47,21 +47,26 @@ module modexpa7_pe_mul
output [31: 0] c_out
);
- localparam LATENCY = 4;
-
- reg [63: 0] abct[1:LATENCY];
-
- assign p = abct[LATENCY][31: 0];
- assign c_out = abct[LATENCY][63:32];
- wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b};
- wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t};
-
- integer i;
- always @(posedge clk)
- //
- for (i=1; i<=LATENCY; i=i+1)
- abct[i] <= (i == 1) ? ab + ct : abct[i-1];
+ //
+ // Include Primitive Selector
+ //
+ `include "modexpa7_pe_settings.v"
+
+
+ //
+ // Instantiate Vendor/Generic Primitive
+ //
+ `MULTIPLIER32_PRIMITIVE multiplier32_inst
+ (
+ .clk(clk),
+ .a(a),
+ .b(b),
+ .t(t),
+ .c_in(c_in),
+ .p(p),
+ .c_out(c_out)
+ );
endmodule