diff options
Diffstat (limited to 'src/rtl/pe/modexpa7_pe_mul.v')
| -rw-r--r-- | src/rtl/pe/modexpa7_pe_mul.v | 41 |
1 files changed, 14 insertions, 27 deletions
diff --git a/src/rtl/pe/modexpa7_pe_mul.v b/src/rtl/pe/modexpa7_pe_mul.v index e56d152..ff15981 100644 --- a/src/rtl/pe/modexpa7_pe_mul.v +++ b/src/rtl/pe/modexpa7_pe_mul.v @@ -47,34 +47,21 @@ module modexpa7_pe_mul output [31: 0] c_out
);
- reg [31: 0] a_reg1;
- reg [31: 0] b_reg1;
- reg [31: 0] t_reg1;
- reg [31: 0] t_reg2;
- reg [31: 0] t_reg3;
- reg [31: 0] c_reg1;
- reg [31: 0] c_reg2;
-
- reg [63: 0] ab_reg;
- reg [63: 0] abc_reg;
- reg [63: 0] abct_reg;
-
- assign p = abct_reg[31: 0];
- assign c_out = abct_reg[63:32];
-
- always @(posedge clk) begin
- a_reg1 <= a;
- b_reg1 <= b;
- c_reg1 <= c_in;
- c_reg2 <= c_reg1;
- t_reg1 <= t;
- t_reg2 <= t_reg1;
- t_reg3 <= t_reg2;
+ localparam LATENCY = 4;
- ab_reg <= {{32{1'b0}}, a_reg1} * {{32{1'b0}}, b_reg1};
- abc_reg <= ab_reg + {{32{1'b0}}, c_reg2};
- abct_reg <= abc_reg + {{32{1'b0}}, t_reg3};
- end
+ reg [63: 0] abct[1:LATENCY];
+
+ assign p = abct[LATENCY][31: 0];
+ assign c_out = abct[LATENCY][63:32];
+
+ wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b};
+ wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t};
+
+ integer i;
+ always @(posedge clk)
+ //
+ for (i=1; i<=LATENCY; i=i+1)
+ abct[i] <= (i == 1) ? ab + ct : abct[i-1];
endmodule
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