diff options
Diffstat (limited to 'src/rtl/modexpa7_systolic_multiplier_array.v')
| -rw-r--r-- | src/rtl/modexpa7_systolic_multiplier_array.v | 72 |
1 files changed, 56 insertions, 16 deletions
diff --git a/src/rtl/modexpa7_systolic_multiplier_array.v b/src/rtl/modexpa7_systolic_multiplier_array.v index 22d5aaf..754203d 100644 --- a/src/rtl/modexpa7_systolic_multiplier_array.v +++ b/src/rtl/modexpa7_systolic_multiplier_array.v @@ -195,11 +195,15 @@ module modexpa7_systolic_multiplier_array # wire shreg_done_load = shreg_load[syst_cnt_last]; wire shreg_done_latency = shreg_latency[SYSTOLIC_PE_LATENCY]; - wire shreg_done_unload = shreg_unload[syst_cnt_last]; - + wire shreg_done_unload = shreg_unload[syst_cnt_last];
+ reg shreg_now_loading; reg shreg_now_latency; reg shreg_now_unloading; +
+ reg shreg_done_latency_dly;
+ always @(posedge clk)
+ shreg_done_latency_dly <= shreg_done_latency;
always @(posedge clk) // @@ -257,17 +261,22 @@ module modexpa7_systolic_multiplier_array # reg fifo_c_rst; reg fifo_t_rst; - wire fifo_c_wren; + reg fifo_c_wren; wire fifo_c_rden; - wire fifo_t_wren; + reg fifo_t_wren; wire fifo_t_rden; - wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_c_din; + reg [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_c_din; wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_c_dout; wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_t_din; wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_t_dout; +
+ wire [32 * 1 - 1 : 0] fifo_t_din_msb;
+ reg [32 * (SYSTOLIC_ARRAY_LENGTH - 1) - 1 : 0] fifo_t_din_lsb;
+
+ assign fifo_t_din = {fifo_t_din_msb, fifo_t_din_lsb}; modexpa7_simple_fifo # ( @@ -317,10 +326,26 @@ module modexpa7_systolic_multiplier_array # // assign pe_c_in[i] = fifo_c_dout[32 * (i + 1) - 1 -: 32]; assign pe_t[i] = fifo_t_dout[32 * (i + 1) - 1 -: 32];
+ //
+ always @(posedge clk)
+ fifo_c_din[32 * (i + 1) - 1 -: 32] <= pe_c_out[i];
+ // + end
+ // + endgenerate
+
+ generate for (i=1; i<SYSTOLIC_ARRAY_LENGTH; i=i+1)
+ // + begin : gen_modexpa7_fifo_t_lsb
+ //
+ always @(posedge clk)
+ fifo_t_din_lsb[32 * i - 1 -: 32] <= pe_p[i];
// end
// - endgenerate + endgenerate
+
+ assign fifo_t_din_msb = shreg_now_unloading ? pe_p[0] : 32'd0; /*
@@ -340,6 +365,15 @@ module modexpa7_systolic_multiplier_array # FSM_STATE_MULT_CRUNCH: if (shreg_done_load) fifo_t_rst <= 1'b0; endcase
+ /*
+ *
+ */
+ assign fifo_c_rden = shreg_now_loading;
+ assign fifo_t_rden = shreg_now_loading;
+
+ always @(posedge clk) fifo_c_wren <= shreg_now_unloading; + always @(posedge clk) fifo_t_wren <= shreg_now_unloading; +
/*
* Block Memory Interface
@@ -390,16 +424,22 @@ module modexpa7_systolic_multiplier_array # -// /*
-// *
-// */
-// always @(posedge clk)
-// //
-// case (fsm_next_state)
-// FSM_STATE_MULT_RELOAD: p_wren <= 1'b1;
-// default: p_wren <= 1'b0;
-// endcase
-//
+ /*
+ *
+ */
+ always @(posedge clk)
+ //
+ case (fsm_next_state)
+ FSM_STATE_MULT_RELOAD: p_wren <= 1'b1;
+ default: p_wren <= 1'b0;
+ endcase
+
+
+ always @(posedge clk) + // + if ((fsm_state == FSM_STATE_MULT_CRUNCH) && shreg_done_latency_dly) + p_data_in <= pe_p[0]; +
/*
* Block Memory Address Control
*/
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