diff options
Diffstat (limited to 'src/rtl/modexpa7_systolic_multiplier_array.v')
| -rw-r--r-- | src/rtl/modexpa7_systolic_multiplier_array.v | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/rtl/modexpa7_systolic_multiplier_array.v b/src/rtl/modexpa7_systolic_multiplier_array.v index 754203d..3280010 100644 --- a/src/rtl/modexpa7_systolic_multiplier_array.v +++ b/src/rtl/modexpa7_systolic_multiplier_array.v @@ -48,6 +48,8 @@ module modexpa7_systolic_multiplier_array # input ena, output rdy, + input crt,
+
output [OPERAND_ADDR_WIDTH - SYSTOLIC_ARRAY_POWER - 1 : 0] loader_addr_rd, input [ 32 * (2 ** SYSTOLIC_ARRAY_POWER) - 1 : 0] pe_a_wide,
@@ -385,6 +387,8 @@ module modexpa7_systolic_multiplier_array # // the very last address
wire [OPERAND_ADDR_WIDTH - 1 : 0] bram_addr_last = n_num_words_latch;
+ wire [OPERAND_ADDR_WIDTH - 1 : 0] bram_addr_last_crt =
+ {n_num_words_latch[OPERAND_ADDR_WIDTH-2:0], 1'b1};
wire [OPERAND_ADDR_WIDTH : 0] bram_addr_ext_last = p_num_words_latch;
// registers
@@ -398,8 +402,9 @@ module modexpa7_systolic_multiplier_array # wire [OPERAND_ADDR_WIDTH : 0] p_addr_next = p_addr + 1'b1;
// handy flags
- wire a_addr_done = (a_addr == bram_addr_last) ? 1'b1 : 1'b0;
- wire p_addr_done = (p_addr == bram_addr_ext_last) ? 1'b1 : 1'b0;
+ wire a_addr_done = (a_addr == bram_addr_last) ? 1'b1 : 1'b0;
+ wire a_addr_done_crt = (a_addr == bram_addr_last_crt) ? 1'b1 : 1'b0;
+ wire p_addr_done = (p_addr == bram_addr_ext_last) ? 1'b1 : 1'b0;
// map top-level ports to internal registers
assign a_bram_addr = a_addr;
@@ -452,7 +457,7 @@ module modexpa7_systolic_multiplier_array # //
case (fsm_next_state) FSM_STATE_MULT_START: a_addr <= bram_addr_zero; - FSM_STATE_MULT_RELOAD: a_addr <= !a_addr_done ? a_addr_next : a_addr; + FSM_STATE_MULT_RELOAD: crt ? //a_addr <= !a_addr_done ? a_addr_next : a_addr; endcase // end |