diff options
Diffstat (limited to 'src/rtl/modexpa7_systolic_multiplier.v')
| -rw-r--r-- | src/rtl/modexpa7_systolic_multiplier.v | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/rtl/modexpa7_systolic_multiplier.v b/src/rtl/modexpa7_systolic_multiplier.v index 7293998..444693d 100644 --- a/src/rtl/modexpa7_systolic_multiplier.v +++ b/src/rtl/modexpa7_systolic_multiplier.v @@ -57,6 +57,8 @@ module modexpa7_systolic_multiplier # input ena, output rdy, +
+ input reduce_only,
output [OPERAND_ADDR_WIDTH-1:0] a_bram_addr, output [OPERAND_ADDR_WIDTH-1:0] b_bram_addr, @@ -155,7 +157,8 @@ module modexpa7_systolic_multiplier # * Parameters Latch */ reg [OPERAND_ADDR_WIDTH-1:0] n_num_words_latch; - reg [OPERAND_ADDR_WIDTH :0] p_num_words_latch; + reg [OPERAND_ADDR_WIDTH :0] p_num_words_latch;
+ reg reduce_only_latch; // save number of words in n when new operation starts always @(posedge clk) @@ -163,7 +166,12 @@ module modexpa7_systolic_multiplier # if ((fsm_state == FSM_STATE_IDLE) && ena_trig) n_num_words_latch <= n_num_words; + always @(posedge clk)
+ //
+ if ((fsm_state == FSM_STATE_IDLE) && ena_trig)
+ reduce_only_latch <= reduce_only;
+
/*
* Multiplication Phase
*/
@@ -174,6 +182,7 @@ module modexpa7_systolic_multiplier # reg [ 1: 0] mult_phase;
+ wire mult_phase_ab = (mult_phase == MULT_PHASE_A_B) ? 1'b1 : 1'b0;
wire mult_phase_done = (mult_phase == MULT_PHASE_STALL) ? 1'b1 : 1'b0;
always @(posedge clk) @@ -296,6 +305,7 @@ module modexpa7_systolic_multiplier # wire [OPERAND_ADDR_WIDTH :0] bram_addr_ext_last = {n_num_words_latch, 1'b1}; // address registers
+ wire [OPERAND_ADDR_WIDTH-1:0] a_addr;
reg [OPERAND_ADDR_WIDTH-1:0] b_addr; reg [OPERAND_ADDR_WIDTH-1:0] n_addr; wire [OPERAND_ADDR_WIDTH :0] p_addr_ext_wr; @@ -570,8 +580,9 @@ module modexpa7_systolic_multiplier # MULT_PHASE_Q_N: p_num_words_latch <= {n_num_words_latch, 1'b1}; endcase
- assign n_coeff_bram_addr = a_bram_addr;
- assign q_addr_rd = a_bram_addr;
+ assign a_bram_addr = a_addr;
+ assign n_coeff_bram_addr = a_addr;
+ assign q_addr_rd = a_addr;
reg [31: 0] a_data_out;
@@ -597,12 +608,14 @@ module modexpa7_systolic_multiplier # .ena (pe_array_ena), .rdy (pe_array_rdy), + .crt (reduce_only_latch && mult_phase_ab),
+
.loader_addr_rd (loader_addr_rd),
.pe_a_wide ({SYSTOLIC_ARRAY_LENGTH{a_data_out}}),
.pe_b_wide (pe_b_wide),
- .a_bram_addr (a_bram_addr),
+ .a_bram_addr (a_addr),
.p_bram_addr (p_addr_ext_wr), .p_bram_in (p_data_in), |