diff options
Diffstat (limited to 'src/rtl/modexpa7_systolic_multiplier.v')
| -rw-r--r-- | src/rtl/modexpa7_systolic_multiplier.v | 51 |
1 files changed, 12 insertions, 39 deletions
diff --git a/src/rtl/modexpa7_systolic_multiplier.v b/src/rtl/modexpa7_systolic_multiplier.v index 378dc63..f53354e 100644 --- a/src/rtl/modexpa7_systolic_multiplier.v +++ b/src/rtl/modexpa7_systolic_multiplier.v @@ -49,7 +49,7 @@ module modexpa7_systolic_multiplier # //
// Explain.
//
- parameter SYSTOLIC_ARRAY_POWER = 2
+ parameter SYSTOLIC_ARRAY_POWER = 1
)
(
input clk,
@@ -597,12 +597,13 @@ module modexpa7_systolic_multiplier # //
// Systolic Array of Processing Elements
//
- reg [31: 0] pe_a [0:SYSTOLIC_ARRAY_LENGTH-1];
- reg [31: 0] pe_b [0:SYSTOLIC_ARRAY_LENGTH-1];
- wire [31: 0] pe_t [0:SYSTOLIC_ARRAY_LENGTH-1];
- wire [31: 0] pe_c_in [0:SYSTOLIC_ARRAY_LENGTH-1];
- wire [31: 0] pe_p [0:SYSTOLIC_ARRAY_LENGTH-1];
- wire [31: 0] pe_c_out[0:SYSTOLIC_ARRAY_LENGTH-1];
+ reg [31: 0] pe_a [0:SYSTOLIC_ARRAY_LENGTH-1];
+ reg [31: 0] pe_b [0:SYSTOLIC_ARRAY_LENGTH-1];
+ wire [31: 0] pe_t [0:SYSTOLIC_ARRAY_LENGTH-1];
+ wire [31: 0] pe_c_in [0:SYSTOLIC_ARRAY_LENGTH-1];
+ wire [31: 0] pe_p [0:SYSTOLIC_ARRAY_LENGTH-1];
+ wire [31: 0] pe_c_out [0:SYSTOLIC_ARRAY_LENGTH-1];
+ reg [31: 0] pe_c_out_dly[0:SYSTOLIC_ARRAY_LENGTH-1];
//
@@ -657,34 +658,6 @@ module modexpa7_systolic_multiplier # .d_out (fifo_t_dout)
);
- /*
- ip_fifo_t fifo_t
- (
- .clk (clk),
- .srst (fifo_t_rst),
- .wr_en (fifo_t_wren),
- .din (fifo_t_din),
- .rd_en (fifo_t_rden),
- .dout (fifo_t_dout),
- .full (),
- .empty ()
- );
- */
-
- /**/
- /*
- ip_fifo_c fifo_c
- (
- .clk (clk),
- .srst (fifo_c_rst),
- .wr_en (fifo_c_wren),
- .din (fifo_c_din),
- .rd_en (fifo_c_rden),
- .dout (fifo_c_dout),
- .full (debug_fifo_full),
- .empty (debug_fifo_empty)
- );*/
-
generate for (i=0; i<SYSTOLIC_ARRAY_LENGTH; i=i+1)
begin : modexpa7_systolic_pe_multiplier
modexpa7_systolic_pe systolic_pe_inst
@@ -699,7 +672,8 @@ module modexpa7_systolic_multiplier # );
assign pe_c_in[i] = fifo_c_dout[32 * (i + 1) - 1 -: 32];
assign pe_t[i] = fifo_t_dout[32 * (i + 1) - 1 -: 32];
- assign fifo_c_din[32 * (i + 1) - 1 -: 32] = pe_c_out[i];
+ assign fifo_c_din[32 * (i + 1) - 1 -: 32] = pe_c_out_dly[i];
+ always @(posedge clk) pe_c_out_dly[i] <= pe_c_out[i];
end
endgenerate
@@ -814,11 +788,10 @@ module modexpa7_systolic_multiplier # always @(posedge clk)
shreg_now_unloading_dly <= shreg_now_unloading;
- assign fifo_c_wren = shreg_now_unloading;
+ assign fifo_c_wren = shreg_now_unloading_dly;
assign fifo_c_rden = shreg_now_loading;
- assign fifo_t_wren = shreg_now_unloading_dly;
-
+ assign fifo_t_wren = shreg_now_unloading_dly;
assign fifo_t_rden = shreg_now_loading;
|