diff options
Diffstat (limited to 'src/rtl/modexpa7_simple_fifo.v')
| -rw-r--r-- | src/rtl/modexpa7_simple_fifo.v | 141 |
1 files changed, 3 insertions, 138 deletions
diff --git a/src/rtl/modexpa7_simple_fifo.v b/src/rtl/modexpa7_simple_fifo.v index 1580e38..5f61d13 100644 --- a/src/rtl/modexpa7_simple_fifo.v +++ b/src/rtl/modexpa7_simple_fifo.v @@ -45,8 +45,8 @@ module modexpa7_simple_fifo # // always @(posedge clk) // - if (rst) ptr_wr <= PTR_ZERO; - else if (wr_en) ptr_wr <= ptr_wr + 1'b1; + if (wr_en) ptr_wr <= ptr_wr + 1'b1; + else if (rst) ptr_wr <= PTR_ZERO; // // Read Pointer @@ -69,142 +69,7 @@ module modexpa7_simple_fifo # // always @(posedge clk) // - if (!rst && wr_en) fifo[ptr_wr] <= d_in; + if (wr_en) fifo[ptr_wr] <= d_in; -/* -generic_dpram #(aw,dw) u0( - .rclk( clk ), - .rrst( !rst ), - .rce( 1'b1 ), - .oe( 1'b1 ), - .raddr( rp ), - .do( dout ), - .wclk( clk ), - .wrst( !rst ), - .wce( 1'b1 ), - .we( we ), - .waddr( wp ), - .di( din ) - ); - -//////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) wp <= #1 {aw{1'b0}}; - else - if(clr) wp <= #1 {aw{1'b0}}; - else - if(we) wp <= #1 wp_pl1; - -assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1}; -assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10}; - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) rp <= #1 {aw{1'b0}}; - else - if(clr) rp <= #1 {aw{1'b0}}; - else - if(re) rp <= #1 rp_pl1; - -assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1}; - -//////////////////////////////////////////////////////////////////// -// -// Combinatorial Full & Empty Flags -// - -assign empty = ((wp == rp) & !gb); -assign full = ((wp == rp) & gb); - -// Guard Bit ... -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) gb <= #1 1'b0; - else - if(clr) gb <= #1 1'b0; - else - if((wp_pl1 == rp) & we) gb <= #1 1'b1; - else - if(re) gb <= #1 1'b0; - -//////////////////////////////////////////////////////////////////// -// -// Registered Full & Empty Flags -// - -// Guard Bit ... -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) gb2 <= #1 1'b0; - else - if(clr) gb2 <= #1 1'b0; - else - if((wp_pl2 == rp) & we) gb2 <= #1 1'b1; - else - if((wp != rp) & re) gb2 <= #1 1'b0; - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) full_r <= #1 1'b0; - else - if(clr) full_r <= #1 1'b0; - else - if(we & ((wp_pl1 == rp) & gb2) & !re) full_r <= #1 1'b1; - else - if(re & ((wp_pl1 != rp) | !gb2) & !we) full_r <= #1 1'b0; - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) empty_r <= #1 1'b1; - else - if(clr) empty_r <= #1 1'b1; - else - if(we & ((wp != rp_pl1) | gb2) & !re) empty_r <= #1 1'b0; - else - if(re & ((wp == rp_pl1) & !gb2) & !we) empty_r <= #1 1'b1; - -//////////////////////////////////////////////////////////////////// -// -// Combinatorial Full_n & Empty_n Flags -// - -assign empty_n = cnt < n; -assign full_n = !(cnt < (max_size-n+1)); -assign level = {2{cnt[aw]}} | cnt[aw-1:aw-2]; - -// N entries status -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) cnt <= #1 {aw+1{1'b0}}; - else - if(clr) cnt <= #1 {aw+1{1'b0}}; - else - if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1}; - else - if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1}; - -//////////////////////////////////////////////////////////////////// -// -// Registered Full_n & Empty_n Flags -// - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) empty_n_r <= #1 1'b1; - else - if(clr) empty_n_r <= #1 1'b1; - else - if(we & (cnt >= (n-1) ) & !re) empty_n_r <= #1 1'b0; - else - if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1; - -always @(posedge clk `SC_FIFO_ASYNC_RESET) - if(!rst) full_n_r <= #1 1'b0; - else - if(clr) full_n_r <= #1 1'b0; - else - if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1; - else - if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0; -*/ - - endmodule |