diff options
Diffstat (limited to 'src/rtl/modexpa7_exponentiator.v')
| -rw-r--r-- | src/rtl/modexpa7_exponentiator.v | 183 |
1 files changed, 122 insertions, 61 deletions
diff --git a/src/rtl/modexpa7_exponentiator.v b/src/rtl/modexpa7_exponentiator.v index 93c8047..c50a881 100644 --- a/src/rtl/modexpa7_exponentiator.v +++ b/src/rtl/modexpa7_exponentiator.v @@ -456,109 +456,134 @@ module modexpa7_exponentiator # // d_addr
//
case (fsm_next_state)
- FSM_STATE_EXP_CALC_1: d_addr <= bit_cnt[OPERAND_ADDR_WIDTH+4:5];
+ FSM_STATE_EXP_CALC_1: d_addr <= bit_cnt[OPERAND_ADDR_WIDTH+4:5];
endcase
//
// f_addr
//
case (fsm_next_state)
- FSM_STATE_MUL_INIT_1: f_addr <= bram_addr_zero;
+ FSM_STATE_MUL_INIT_1: f_addr <= bram_addr_zero;
FSM_STATE_MUL_INIT_2,
FSM_STATE_MUL_INIT_3,
- FSM_STATE_MUL_INIT_4: f_addr <= !f_addr_done ? f_addr_next : f_addr;
+ FSM_STATE_MUL_INIT_4: f_addr <= !f_addr_done ? f_addr_next : f_addr;
+ //
+ FSM_STATE_CRT_INIT_B_1: f_addr <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_B_2,
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4: f_addr <= !f_addr_done ? f_addr_next : f_addr;
+ //
endcase
//
// r_addr
//
case (fsm_next_state)
- FSM_STATE_EXP_SAVE_3: r_addr <= bram_addr_zero;
- FSM_STATE_EXP_SAVE_4: r_addr <= r_addr_next;
+ FSM_STATE_EXP_SAVE_3: r_addr <= bram_addr_zero;
+ FSM_STATE_EXP_SAVE_4: r_addr <= r_addr_next;
endcase
//
// p_addr_wr
//
case (fsm_next_state)
//
- FSM_STATE_MUL_INIT_3: p_addr_wr <= bram_addr_zero;
- FSM_STATE_MUL_INIT_4: p_addr_wr <= p_addr_wr_next;
+ FSM_STATE_MUL_INIT_3: p_addr_wr <= bram_addr_zero;
+ FSM_STATE_MUL_INIT_4: p_addr_wr <= p_addr_wr_next;
+ //
+ FSM_STATE_CRT_INIT_B_3: p_addr_wr <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_B_4: p_addr_wr <= p_addr_wr_next;
//
- FSM_STATE_EXP_INIT_3: p_addr_wr <= bram_addr_zero;
- FSM_STATE_EXP_INIT_4: p_addr_wr <= p_addr_wr_next;
+ FSM_STATE_EXP_INIT_3: p_addr_wr <= bram_addr_zero;
+ FSM_STATE_EXP_INIT_4: p_addr_wr <= p_addr_wr_next;
//
- FSM_STATE_EXP_FILL_3: p_addr_wr <= bram_addr_zero;
- FSM_STATE_EXP_FILL_4: p_addr_wr <= p_addr_wr_next;
+ FSM_STATE_EXP_FILL_3: p_addr_wr <= bram_addr_zero;
+ FSM_STATE_EXP_FILL_4: p_addr_wr <= p_addr_wr_next;
endcase
//
// t0_addr
//
case (fsm_next_state)
- FSM_STATE_EXP_LOAD_3: t0_addr <= bram_addr_zero;
- FSM_STATE_EXP_LOAD_4: t0_addr <= t0_addr_next;
+ FSM_STATE_EXP_LOAD_3: t0_addr <= bram_addr_zero;
+ FSM_STATE_EXP_LOAD_4: t0_addr <= t0_addr_next;
//
- FSM_STATE_EXP_FILL_1: t0_addr <= bram_addr_zero;
+ FSM_STATE_EXP_FILL_1: t0_addr <= bram_addr_zero;
FSM_STATE_EXP_FILL_2,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: t0_addr <= !t0_addr_done ? t0_addr_next : t0_addr;
+ FSM_STATE_EXP_FILL_4: t0_addr <= !t0_addr_done ? t0_addr_next : t0_addr;
endcase
//
// t1_addr
//
case (fsm_next_state)
- FSM_STATE_EXP_INIT_3: t1_addr <= bram_addr_zero;
- FSM_STATE_EXP_INIT_4: t1_addr <= t1_addr_next;
+ FSM_STATE_EXP_INIT_3: t1_addr <= bram_addr_zero;
+ FSM_STATE_EXP_INIT_4: t1_addr <= t1_addr_next;
//
- FSM_STATE_EXP_LOAD_1: t1_addr <= bram_addr_zero;
+ FSM_STATE_EXP_LOAD_1: t1_addr <= bram_addr_zero;
FSM_STATE_EXP_LOAD_2,
FSM_STATE_EXP_LOAD_3,
- FSM_STATE_EXP_LOAD_4: t1_addr <= !t1_addr_done ? t1_addr_next : t1_addr;
+ FSM_STATE_EXP_LOAD_4: t1_addr <= !t1_addr_done ? t1_addr_next : t1_addr;
//
- FSM_STATE_EXP_FILL_3: t1_addr <= bram_addr_zero;
- FSM_STATE_EXP_FILL_4: t1_addr <= t1_addr_next;
+ FSM_STATE_EXP_FILL_3: t1_addr <= bram_addr_zero;
+ FSM_STATE_EXP_FILL_4: t1_addr <= t1_addr_next;
//
- FSM_STATE_EXP_SAVE_1: t1_addr <= bram_addr_zero;
+ FSM_STATE_EXP_SAVE_1: t1_addr <= bram_addr_zero;
FSM_STATE_EXP_SAVE_2,
FSM_STATE_EXP_SAVE_3,
- FSM_STATE_EXP_SAVE_4: t1_addr <= !t1_addr_done ? t1_addr_next : t1_addr;
+ FSM_STATE_EXP_SAVE_4: t1_addr <= !t1_addr_done ? t1_addr_next : t1_addr;
endcase
//
// t2_addr_wr
//
case (fsm_next_state)
//
- FSM_STATE_MUL_INIT_3: t2_addr_wr <= bram_addr_zero;
- FSM_STATE_MUL_INIT_4: t2_addr_wr <= t2_addr_wr_next;
+ FSM_STATE_MUL_INIT_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_MUL_INIT_4: t2_addr_wr <= t2_addr_wr_next;
//
- FSM_STATE_CRT_INIT_A_3: t2_addr_wr <= bram_addr_zero;
- FSM_STATE_CRT_INIT_A_4: t2_addr_wr <= t2_addr_wr_next;
+ FSM_STATE_CRT_INIT_A_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_A_4: t2_addr_wr <= t2_addr_wr_next;
//
- FSM_STATE_EXP_INIT_3: t2_addr_wr <= bram_addr_zero;
- FSM_STATE_EXP_INIT_4: t2_addr_wr <= t2_addr_wr_next;
+ FSM_STATE_CRT_INIT_B_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_B_4: t2_addr_wr <= t2_addr_wr_next;
//
- FSM_STATE_EXP_FILL_3: t2_addr_wr <= bram_addr_zero;
- FSM_STATE_EXP_FILL_4: t2_addr_wr <= t2_addr_wr_next;
+ FSM_STATE_CRT_INIT_C_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_C_4: t2_addr_wr <= t2_addr_wr_next;
+ //
+ FSM_STATE_EXP_INIT_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_EXP_INIT_4: t2_addr_wr <= t2_addr_wr_next;
+ //
+ FSM_STATE_EXP_FILL_3: t2_addr_wr <= bram_addr_zero;
+ FSM_STATE_EXP_FILL_4: t2_addr_wr <= t2_addr_wr_next;
endcase
//
// pp_addr_rd
//
case (fsm_next_state)
- FSM_STATE_EXP_FILL_1: pp_addr_rd <= bram_addr_zero;
+ FSM_STATE_EXP_FILL_1: pp_addr_rd <= bram_addr_zero;
FSM_STATE_EXP_FILL_2,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: pp_addr_rd <= !pp_addr_rd_done ? pp_addr_rd_next : pp_addr_rd;
+ FSM_STATE_EXP_FILL_4: pp_addr_rd <= !pp_addr_rd_done ? pp_addr_rd_next : pp_addr_rd;
endcase
//
// tp_addr_rd
//
case (fsm_next_state)
- FSM_STATE_EXP_INIT_1: tp_addr_rd <= bram_addr_zero;
+ FSM_STATE_EXP_INIT_1: tp_addr_rd <= bram_addr_zero;
FSM_STATE_EXP_INIT_2,
FSM_STATE_EXP_INIT_3,
- FSM_STATE_EXP_INIT_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
+ FSM_STATE_EXP_INIT_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
+ //
+ FSM_STATE_CRT_INIT_B_1: tp_addr_rd <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_B_2,
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
//
- FSM_STATE_EXP_FILL_1: tp_addr_rd <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_C_1: tp_addr_rd <= bram_addr_zero;
+ FSM_STATE_CRT_INIT_C_2,
+ FSM_STATE_CRT_INIT_C_3,
+ FSM_STATE_CRT_INIT_C_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
+ //
+ FSM_STATE_EXP_FILL_1: tp_addr_rd <= bram_addr_zero;
FSM_STATE_EXP_FILL_2,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
+ FSM_STATE_EXP_FILL_4: tp_addr_rd <= !tp_addr_rd_done ? tp_addr_rd_next : tp_addr_rd;
endcase
//
end
@@ -573,8 +598,8 @@ module modexpa7_exponentiator # //
case (fsm_next_state)
FSM_STATE_EXP_SAVE_3,
- FSM_STATE_EXP_SAVE_4: r_wren <= 1'b1;
- default: r_wren <= 1'b0;
+ FSM_STATE_EXP_SAVE_4: r_wren <= 1'b1;
+ default: r_wren <= 1'b0;
endcase
//
// p_wren
@@ -582,19 +607,21 @@ module modexpa7_exponentiator # case (fsm_next_state)
FSM_STATE_MUL_INIT_3,
FSM_STATE_MUL_INIT_4,
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4,
FSM_STATE_EXP_INIT_3,
FSM_STATE_EXP_INIT_4,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: p_wren <= 1'b1;
- default: p_wren <= 1'b0;
+ FSM_STATE_EXP_FILL_4: p_wren <= 1'b1;
+ default: p_wren <= 1'b0;
endcase
//
// t0_wren
//
case (fsm_next_state)
FSM_STATE_EXP_LOAD_3,
- FSM_STATE_EXP_LOAD_4: t0_wren <= 1'b1;
- default: t0_wren <= 1'b0;
+ FSM_STATE_EXP_LOAD_4: t0_wren <= 1'b1;
+ default: t0_wren <= 1'b0;
endcase
//
// t1_wren
@@ -603,8 +630,8 @@ module modexpa7_exponentiator # FSM_STATE_EXP_INIT_3,
FSM_STATE_EXP_INIT_4,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: t1_wren <= 1'b1;
- default: t1_wren <= 1'b0;
+ FSM_STATE_EXP_FILL_4: t1_wren <= 1'b1;
+ default: t1_wren <= 1'b0;
endcase
//
// t2_wren
@@ -614,11 +641,15 @@ module modexpa7_exponentiator # FSM_STATE_MUL_INIT_4,
FSM_STATE_CRT_INIT_A_3,
FSM_STATE_CRT_INIT_A_4,
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4,
+ FSM_STATE_CRT_INIT_C_3,
+ FSM_STATE_CRT_INIT_C_4,
FSM_STATE_EXP_INIT_3,
FSM_STATE_EXP_INIT_4,
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: t2_wren <= 1'b1;
- default: t2_wren <= 1'b0;
+ FSM_STATE_EXP_FILL_4: t2_wren <= 1'b1;
+ default: t2_wren <= 1'b0;
endcase
//
end
@@ -633,8 +664,8 @@ module modexpa7_exponentiator # //
case (fsm_next_state)
FSM_STATE_EXP_SAVE_3,
- FSM_STATE_EXP_SAVE_4: r_data_in <= t1_data_out;
- default: r_data_in <= 32'dX;
+ FSM_STATE_EXP_SAVE_4: r_data_in <= t1_data_out;
+ default: r_data_in <= 32'dX;
endcase
//
// p_data_in
@@ -642,34 +673,37 @@ module modexpa7_exponentiator # case (fsm_next_state)
//
FSM_STATE_MUL_INIT_3,
- FSM_STATE_MUL_INIT_4: p_data_in <= f_bram_out;
+ FSM_STATE_MUL_INIT_4: p_data_in <= f_bram_out;
+ //
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4: p_data_in <= f_bram_out;
//
FSM_STATE_EXP_INIT_3,
- FSM_STATE_EXP_INIT_4: p_data_in <= tp_data_out;
+ FSM_STATE_EXP_INIT_4: p_data_in <= tp_data_out;
//
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: p_data_in <= pp_data_out;
+ FSM_STATE_EXP_FILL_4: p_data_in <= pp_data_out;
//
- default: p_data_in <= 32'dX;
+ default: p_data_in <= 32'dX;
endcase
//
// t0_data_in
//
case (fsm_next_state)
FSM_STATE_EXP_LOAD_3,
- FSM_STATE_EXP_LOAD_4: t0_data_in <= t1_data_out;
- default: t0_data_in <= 32'dX;
+ FSM_STATE_EXP_LOAD_4: t0_data_in <= t1_data_out;
+ default: t0_data_in <= 32'dX;
endcase
//
// t1_data_in
//
case (fsm_next_state)
- FSM_STATE_EXP_INIT_3: t1_data_in <= 32'd1;
- FSM_STATE_EXP_INIT_4: t1_data_in <= 32'd0;
+ FSM_STATE_EXP_INIT_3: t1_data_in <= 32'd1;
+ FSM_STATE_EXP_INIT_4: t1_data_in <= 32'd0;
//
FSM_STATE_EXP_FILL_3,
- FSM_STATE_EXP_FILL_4: t1_data_in <= flag_update_r ? tp_data_out : t0_data_out;
- default: t1_data_in <= 32'dX;
+ FSM_STATE_EXP_FILL_4: t1_data_in <= flag_update_r ? tp_data_out : t0_data_out;
+ default: t1_data_in <= 32'dX;
endcase
//
// t2_data_in
@@ -681,7 +715,12 @@ module modexpa7_exponentiator # //
FSM_STATE_CRT_INIT_A_3,
FSM_STATE_CRT_INIT_A_4: t2_data_in <= m_bram_out;
-
+ //
+ FSM_STATE_CRT_INIT_B_3,
+ FSM_STATE_CRT_INIT_B_4: t2_data_in <= tp_data_out;
+ //
+ FSM_STATE_CRT_INIT_C_3,
+ FSM_STATE_CRT_INIT_C_4: t2_data_in <= tp_data_out;
//
FSM_STATE_EXP_INIT_3: t2_data_in <= 32'd1;
FSM_STATE_EXP_INIT_4: t2_data_in <= 32'd0;
@@ -828,7 +867,29 @@ module modexpa7_exponentiator # FSM_STATE_CRT_CALC_A_1: fsm_next_state = FSM_STATE_CRT_CALC_A_2;
FSM_STATE_CRT_CALC_A_2: if (mul_rdy_tp) fsm_next_state = FSM_STATE_CRT_CALC_A_3;
else fsm_next_state = FSM_STATE_CRT_CALC_A_2;
- FSM_STATE_CRT_CALC_A_3: fsm_next_state = FSM_STATE_EXP_INIT_1;
+ FSM_STATE_CRT_CALC_A_3: fsm_next_state = FSM_STATE_CRT_INIT_B_1;
+ //
+ FSM_STATE_CRT_INIT_B_1: fsm_next_state = FSM_STATE_CRT_INIT_B_2;
+ FSM_STATE_CRT_INIT_B_2: fsm_next_state = FSM_STATE_CRT_INIT_B_3;
+ FSM_STATE_CRT_INIT_B_3: fsm_next_state = FSM_STATE_CRT_INIT_B_4;
+ FSM_STATE_CRT_INIT_B_4: if (t2_addr_wr_done) fsm_next_state = FSM_STATE_CRT_CALC_B_1;
+ else fsm_next_state = FSM_STATE_CRT_INIT_B_4;
+ //
+ FSM_STATE_CRT_CALC_B_1: fsm_next_state = FSM_STATE_CRT_CALC_B_2;
+ FSM_STATE_CRT_CALC_B_2: if (mul_rdy_tp) fsm_next_state = FSM_STATE_CRT_CALC_B_3;
+ else fsm_next_state = FSM_STATE_CRT_CALC_B_2;
+ FSM_STATE_CRT_CALC_B_3: fsm_next_state = FSM_STATE_CRT_INIT_C_1;
+ //
+ FSM_STATE_CRT_INIT_C_1: fsm_next_state = FSM_STATE_CRT_INIT_C_2;
+ FSM_STATE_CRT_INIT_C_2: fsm_next_state = FSM_STATE_CRT_INIT_C_3;
+ FSM_STATE_CRT_INIT_C_3: fsm_next_state = FSM_STATE_CRT_INIT_C_4;
+ FSM_STATE_CRT_INIT_C_4: if (t2_addr_wr_done) fsm_next_state = FSM_STATE_CRT_CALC_C_1;
+ else fsm_next_state = FSM_STATE_CRT_INIT_C_4;
+ //
+ FSM_STATE_CRT_CALC_C_1: fsm_next_state = FSM_STATE_CRT_CALC_C_2;
+ FSM_STATE_CRT_CALC_C_2: if (mul_rdy_tp) fsm_next_state = FSM_STATE_CRT_CALC_C_3;
+ else fsm_next_state = FSM_STATE_CRT_CALC_C_2;
+ FSM_STATE_CRT_CALC_C_3: fsm_next_state = FSM_STATE_EXP_INIT_1;
//
//
FSM_STATE_EXP_IDLE: if (ena_trig) fsm_next_state = crt ?
|