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-//======================================================================
-//
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module dsp_multiplier_a7
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- output [63: 0] p
- );
-
- //
- // Split a, b into parts
- //
- wire [16: 0] a_lo = a[16: 0];
- wire [16: 0] b_lo = b[16: 0];
-
- wire [14: 0] a_hi = a[31:17];
- wire [14: 0] b_hi = b[31:17];
-
- //
- // Products
- //
- wire [47: 0] p_dsp1;
- wire [47: 0] p_dsp3;
- wire [47: 0] p_dsp4;
-
- //
- // Cascade p
- //
- wire [47: 0] p_dsp1_chain;
- wire [47: 0] p_dsp2_chain;
- wire [47: 0] p_dsp3_chain;
-
- //
- // Cascade a
- //
- wire [29: 0] a_lo_chain;
- wire [29: 0] a_hi_chain;
-
- //
- // Register parts of p
- //
- genvar i;
- generate for (i=0; i<17; i=i+1)
- begin : FD_gen
- //
- FD #(.INIT (1'b0))
- FD_inst_1
- (
- .C (clk),
- .D (p_dsp1[i]),
- .Q (p[i])
- );
- //
- FD #(.INIT(1'b0))
- FD_inst_2
- (
- .C (clk),
- .D (p_dsp3[i]),
- .Q (p[17+i])
- );
- //
- end
- endgenerate
-
- //
- // Mapping
- //
- assign p[63:34] = p_dsp4[29:0];
-
- //
- // a_lo * b_lo
- //
- DSP48E1 #
- (
- .AREG (1),
- .BREG (1),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (0),
- .ADREG (0),
-
- .INMODEREG (0),
- .OPMODEREG (0),
- .ALUMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .ACASCREG (1),
- .BCASCREG (1),
-
- .A_INPUT ("DIRECT"),
- .B_INPUT ("DIRECT"),
-
- .USE_SIMD ("ONE48"),
- .USE_DPORT ("FALSE"),
- .USE_MULT ("MULTIPLY"),
- .USE_PATTERN_DETECT ("NO_PATDET"),
-
- .SEL_MASK ("MASK"),
- .SEL_PATTERN ("PATTERN"),
-
- .MASK (48'h000000000000),
- .PATTERN (48'h000000000000),
-
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst1
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (1'b1),
- .CEB1 (1'b0),
- .CEB2 (1'b1),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (1'b0),
- .CEP (1'b0),
- .CEAD (1'b0),
-
- .CECTRL (1'b0),
- .CEINMODE (1'b0),
- .CEALUMODE (1'b0),
- .CECARRYIN (1'b0),
-
- .CARRYINSEL (3'b000),
- .ALUMODE (4'b0000),
- .INMODE (5'b00000),
- .OPMODE (7'b0110101),
-
- .A ({{13{1'b0}}, a_lo}),
- .B ({{ 1{1'b0}}, b_lo}),
- .C ({48{1'b0}}),
- .D ({25{1'b0}}),
- .P (p_dsp1),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .ACIN ({30{1'b0}}),
- .BCIN ({18{1'b0}}),
-
- .ACOUT (a_lo_chain),
- .BCOUT (),
-
- .PCIN ({48{1'b0}}),
- .PCOUT (p_dsp1_chain),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .UNDERFLOW (),
- .OVERFLOW ()
- );
-
- //
- // a_lo * b_hi
- //
- DSP48E1 #
- (
- .AREG (0),
- .BREG (1),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (0),
- .ADREG (0),
-
- .INMODEREG (0),
- .OPMODEREG (0),
- .ALUMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .ACASCREG (0),
- .BCASCREG (1),
-
- .A_INPUT ("CASCADE"),
- .B_INPUT ("DIRECT"),
-
- .USE_SIMD ("ONE48"),
- .USE_DPORT ("FALSE"),
- .USE_MULT ("MULTIPLY"),
- .USE_PATTERN_DETECT ("NO_PATDET"),
-
- .SEL_MASK ("MASK"),
- .SEL_PATTERN ("PATTERN"),
-
- .MASK (48'h000000000000),
- .PATTERN (48'h000000000000),
-
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst2
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (1'b0),
- .CEB1 (1'b0),
- .CEB2 (1'b1),
- .CEC (1'b0),
- .CED (1'b0),
- .CEP (1'b0),
- .CEM (1'b0),
- .CEAD (1'b0),
-
- .CECTRL (1'b0),
- .CEINMODE (1'b0),
- .CEALUMODE (1'b0),
- .CECARRYIN (1'b0),
-
- .CARRYINSEL (3'b000),
- .ALUMODE (4'b0000),
- .INMODE (5'b00000),
- .OPMODE (7'b1010101),
-
- .A ({30{1'b0}}),
- .B ({{3{1'b0}}, b_hi}),
- .C ({48{1'b0}}),
- .D ({25{1'b0}}),
- .P (),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .ACIN (a_lo_chain),
- .BCIN ({18{1'b0}}),
-
- .ACOUT (),
- .BCOUT (),
-
- .PCIN (p_dsp1_chain),
- .PCOUT (p_dsp2_chain),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .UNDERFLOW (),
- .OVERFLOW ()
- );
-
- //
- // a_hi * b_lo
- //
- DSP48E1 #
- (
- .AREG (1),
- .BREG (1),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (0),
- .ADREG (0),
-
- .INMODEREG (0),
- .OPMODEREG (0),
- .ALUMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .ACASCREG (1),
- .BCASCREG (1),
-
- .A_INPUT ("DIRECT"),
- .B_INPUT ("DIRECT"),
-
- .USE_SIMD ("ONE48"),
- .USE_DPORT ("FALSE"),
- .USE_MULT ("MULTIPLY" ),
- .USE_PATTERN_DETECT ("NO_PATDET"),
-
- .SEL_MASK ("MASK"),
- .SEL_PATTERN ("PATTERN"),
-
- .MASK (48'h000000000000),
- .PATTERN (48'h000000000000),
-
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst3
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (1'b1),
- .CEB1 (1'b0),
- .CEB2 (1'b1),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (1'b0),
- .CEP (1'b0),
- .CEAD (1'b0),
-
- .CECTRL (1'b0),
- .CEINMODE (1'b0),
- .CEALUMODE (1'b0),
- .CECARRYIN (1'b0),
-
- .CARRYINSEL (3'b000),
- .ALUMODE (4'b0000),
- .INMODE (5'b00000),
- .OPMODE (7'b0010101),
-
- .A ({{15{1'b0}}, a_hi}),
- .B ({{ 1{1'b0}}, b_lo}),
- .C ({48{1'b0}}),
- .D ({25{1'b0}}),
- .P (p_dsp3),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .ACIN ({30{1'b0}}),
- .BCIN ({18{1'b0}}),
-
- .ACOUT (a_hi_chain),
- .BCOUT (),
-
- .PCIN (p_dsp2_chain),
- .PCOUT (p_dsp3_chain),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .UNDERFLOW (),
- .OVERFLOW ()
- );
-
- //
- // a_hi * b_hi
- //
- DSP48E1 #
- (
- .AREG (0),
- .BREG (1),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (1),
- .ADREG (0),
-
- .INMODEREG (0),
- .OPMODEREG (0),
- .ALUMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .ACASCREG (0),
- .BCASCREG (1),
-
- .A_INPUT ("CASCADE"),
- .B_INPUT ("DIRECT"),
-
- .USE_SIMD ("ONE48"),
- .USE_DPORT ("FALSE"),
- .USE_MULT ("MULTIPLY"),
- .USE_PATTERN_DETECT ("NO_PATDET"),
-
- .SEL_MASK ("MASK"),
- .SEL_PATTERN ("PATTERN"),
-
- .MASK (48'h000000000000),
- .PATTERN (48'h000000000000),
-
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst4
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (1'b0),
- .CEB1 (1'b0),
- .CEB2 (1'b1),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (1'b0),
- .CEP (1'b1),
- .CEAD (1'b0),
-
- .CECTRL (1'b0),
- .CEINMODE (1'b0),
- .CEALUMODE (1'b0),
- .CECARRYIN (1'b0),
-
- .CARRYINSEL (3'b000),
- .ALUMODE (4'b0000),
- .INMODE (5'b00000),
- .OPMODE (7'b1010101),
-
- .A ({30{1'b0}}),
- .B ({{3{1'b0}}, b_hi}),
- .C ({48{1'b0}}),
- .D ({25{1'b0}}),
- .P (p_dsp4),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .ACIN (a_hi_chain),
- .BCIN ({18{1'b0}}),
-
- .ACOUT (),
- .BCOUT (),
-
- .PCIN (p_dsp3_chain),
- .PCOUT (),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .UNDERFLOW (),
- .OVERFLOW ()
- );
-
-
-endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 05:04:27 +0000