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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-23 04:10:47 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-23 04:10:47 +0300
commitb33f595c014250072e9d787057293ef685eab5f3 (patch)
tree348d27c613c965e156a94e9be4fb1c984af0de23 /src/stm32/test
parent3ca2b94aae8af47788ec236f624857c15c4e73b1 (diff)
Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes just fine:
10% slices 8% block memory 33% DSPs
Diffstat (limited to 'src/stm32/test')
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