diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-08-09 16:13:45 +0300 |
---|---|---|
committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-08-09 16:13:45 +0300 |
commit | a44bbd3fe1088201401430079f8af52b207eece6 (patch) | |
tree | af8aceafab08cc4204387fae461d07ca4c990b40 /src/rtl/pe/generic/adder32_generic.v | |
parent | 06dadb7faa692831f7353910269ecbdf0dd6b21c (diff) |
Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prevent clashes
with low-level modules in ECDSA multipliers.
We should consolidate all the lowel-level stuff across all the math cores in the future.
Diffstat (limited to 'src/rtl/pe/generic/adder32_generic.v')
-rw-r--r-- | src/rtl/pe/generic/adder32_generic.v | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/src/rtl/pe/generic/adder32_generic.v b/src/rtl/pe/generic/adder32_generic.v deleted file mode 100644 index 10ecfa4..0000000 --- a/src/rtl/pe/generic/adder32_generic.v +++ /dev/null @@ -1,69 +0,0 @@ -//------------------------------------------------------------------------------ -// -// adder32_generic.v -// ----------------------------------------------------------------------------- -// Generic 32-bit adder w/ clock enable.
-// -// Authors: Pavel Shatov -// -// Copyright (c) 2016-2017, NORDUnet A/S -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//------------------------------------------------------------------------------
-
-module adder32_generic
- (
- input clk, // clock
- input ce, // clock enable
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
- - // - // Sum - // - reg [32: 0] s_int;
-
- always @(posedge clk)
- if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
-
- //
- // Output
- //
- assign s = s_int[31:0];
- assign c_out = s_int[32];
-
-
-endmodule
-
-//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------
|