Finished modulus-dependent coefficient calculation module:

 * fixed bug with latency compensation
 * cleaned up Verilog source
 * added 512-bit testbench
 * works in simulator
 * synthesizes without warnings

Changes:
 * made latency of generic processing element configurable

1 files changed, 0 insertions, 57 deletions

diff --git a/src/rtl/modexpa7_factor.v b/src/rtl/modexpa7_factor.v
index 17d4785..510f7af 100644
--- a/src/rtl/modexpa7_factor.v
+++ b/src/rtl/modexpa7_factor.v
@@ -118,63 +118,6 @@ module modexpa7_factor #
 	localparam	[OPERAND_ADDR_WIDTH-1:0]	bram_addr_zero = {OPERAND_ADDR_WIDTH{1'b0}};

 	wire			[OPERAND_ADDR_WIDTH-1:0]	bram_addr_last = n_num_words_latch;

 	

-	

-		//

-		// BRAM Addresses

-		//

-		/*

-	reg	[OPERAND_ADDR_WIDTH-1:0]	f_bram_addr_reg;

-		

-	wire	[OPERAND_ADDR_WIDTH-1:0]	f_bram_addr_next = f_bram_addr + 1'b1;

-	

-	wire										f_bram_addr_done =  (f_bram_addr == bram_addr_last) ? 1'b1 : 1'b0;

-	

-	assign f_bram_addr = f_bram_addr_reg;

-

-		

-	always @(posedge clk)

-		//

-		case (fsm_next_state)

-		

-			FSM_STATE_INIT_ZERO_ADDR:	f_bram_addr_reg <= bram_addr_zero;

-			FSM_STATE_INIT_NEXT_ADDR:	f_bram_addr_reg <= f_bram_addr_next;

-			

-		endcase

-

-	reg	f_bram_en;

-	

-	assign f_bram_wr = f_bram_en;

-	

-	always @(posedge clk)

-		//

-		case (fsm_next_state)

-			

-			FSM_STATE_INIT_ZERO_ADDR,

-			FSM_STATE_INIT_NEXT_ADDR,

-			FSM_STATE_INIT_LAST_ADDR:	f_bram_en <= 1'b1;

-			default:							f_bram_en <= 1'b0;

-			

-		endcase

-	

-	

-	reg	[31: 0]	f_bram_data;

-	

-	assign f_bram_in = f_bram_data;

-	

-	always @(posedge clk)

-		//

-		case (fsm_next_state)

-			FSM_STATE_INIT_ZERO_ADDR:	f_bram_data <= 32'd1;

-			FSM_STATE_INIT_NEXT_ADDR,

-			FSM_STATE_INIT_LAST_ADDR:	f_bram_data <= 32'd0;

-			default:							f_bram_data <= {32{1'bX}};

-			

-		endcase

-		*/

-		

-

-	

-	

 		//

 		// Cycle Counters

 		//