//======================================================================
//
// modexpa7_pe_mul.v
// -----------------------------------------------------------------------------
// Low-level processing element (multiplier).
//
// Authors: Pavel Shatov
//
// Copyright (c) 2017, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module modexpa7_pe_mul
(
input clk,
input [31: 0] a,
input [31: 0] b,
input [31: 0] t,
input [31: 0] c_in,
output [31: 0] p,
output [31: 0] c_out
);
reg [31: 0] a_reg1;
reg [31: 0] b_reg1;
reg [31: 0] t_reg1;
reg [31: 0] t_reg2;
reg [31: 0] t_reg3;
reg [31: 0] c_reg1;
reg [31: 0] c_reg2;
reg [63: 0] ab_reg;
reg [63: 0] abc_reg;
reg [63: 0] abct_reg;
assign p = abct_reg[31: 0];
assign c_out = abct_reg[63:32];
always @(posedge clk) begin
a_reg1 <= a;
b_reg1 <= b;
c_reg1 <= c_in;
c_reg2 <= c_reg1;
t_reg1 <= t;
t_reg2 <= t_reg1;
t_reg3 <= t_reg2;
ab_reg <= {{32{1'b0}}, a_reg1} * {{32{1'b0}}, b_reg1};
abc_reg <= ab_reg + {{32{1'b0}}, c_reg2};
abct_reg <= abc_reg + {{32{1'b0}}, t_reg3};
end
endmodule
//======================================================================
// End of file
//======================================================================