path: root/src/rtl/pe/generic/modexpa7_adder32_generic.v

//------------------------------------------------------------------------------
//
// modexpa7_adder32_generic.v
// -----------------------------------------------------------------------------
// Generic 32-bit adder w/ clock enable.
//
// Authors: Pavel Shatov
//
// Copyright (c) 2016-2017, NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may be
//   used to endorse or promote products derived from this software without
//   specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------

module modexpa7_adder32_generic
	(
		input					clk,		// clock
		input					ce,		// clock enable
		input		[31: 0]	a,			// operand input
		input		[31: 0]	b,			// operand input
		output	[31: 0]	s,			// sum output
		input					c_in,		// carry input
		output				c_out		// carry output
	);
	
		//
		// Sum
		//
	reg	[32: 0]	s_int;
	
	always @(posedge clk)
		if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
		
		//
		// Output
		//
	assign s = s_int[31:0];
	assign c_out = s_int[32];
	
		
endmodule

//------------------------------------------------------------------------------
// End-of-File
//------------------------------------------------------------------------------