core/math/modexp - Modular exponentiation core

Age	Commit message (Collapse)	Author
2015-12-13	whack copyrightsHEAD master	Paul Selkirk

2015-06-26	Changed modexp core to use explicit exponent length to allow removal of ↵	Joachim Strömbergson
	padding of exponent and improving performance. Updated testbenches to match the changed lengths inside the device under test.
2015-06-02	Refactored into core and top.	Joachim Strömbergson

2015-05-20	Changed to using modexp length register and removed the common length register.	Joachim Strömbergson

2015-04-27	Updating modexp core to v 0.50. This version contains a working core that ↵	Joachim Strömbergson
	can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
2015-04-24	(1) Adding auto generated testbench for verilog. (2) Update of the test ↵	Joachim Strömbergson
	generator. (3) Update of the Makefile to run test generator.