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padding of exponent and improving performance. Updated testbenches to match the changed lengths inside the device under test.
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can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
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generator. (3) Update of the Makefile to run test generator.
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