| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-12-13 | whack copyrightsHEADmaster | Paul Selkirk | |
| 2015-06-03 | Adding test for for public exponent operation based on Rob 1024 bit key. | Joachim Strömbergson | |
| 2015-06-02 | Minor fix for better layout. | Joachim Strömbergson | |
| 2015-06-02 | Padded Rob 1024 test with one 32-bit word. This makes the model work for the ↵ | Joachim Strömbergson | |
| test case. | |||
| 2015-06-02 | Cleanup of result checking code to make it easier to see any errors. | Joachim Strömbergson | |
| 2015-06-02 | Fixd nits in test case. Added simple line break to clean up. | Joachim Strömbergson | |
| 2015-06-02 | Adding 1024 bit test case from Rob to verify that it works in the model. | Joachim Strömbergson | |
| 2015-05-22 | Updated the C model with version of modexp that supports explicit, separate ↵ | Joachim Strömbergson | |
| lengths for exponent and modulus. Also added new test cases, cleaned up code etc. | |||
| 2015-05-22 | Removed obsoleted temp parameter. | Joachim Strömbergson | |
| 2015-05-22 | Removed file that should not have been in the repo. | Joachim Strömbergson | |
| 2015-04-27 | Updating modexp core to v 0.50. This version contains a working core that ↵ | Joachim Strömbergson | |
| can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices. | |||
| 2015-04-24 | (1) Adding auto generated testbench for verilog. (2) Update of the test ↵ | Joachim Strömbergson | |
| generator. (3) Update of the Makefile to run test generator. | |||
| 2015-03-13 | Adding c model for the modexp core. | Joachim Strömbergson | |
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index : core/math/modexp | |
| Modular exponentiation core | git repositories |
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