Age | Commit message (Collapse) | Author |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cores
|
|
|
|
|
|
|
|
|
|
|
|
|
|
test case.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
exponent and modulus, message.
|
|
lengths for exponent and modulus. Also added new test cases, cleaned up code etc.
|
|
|
|
|
|
value. Moved reset of start reg to beginning of FSM.
|
|
bigger test case.
|
|
|
|
|
|
modulus is updated. Minor cleanup.
|
|
|
|
|
|
|
|
can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
|
|
generator. (3) Update of the Makefile to run test generator.
|
|
|
|
|
|
|
|
Update of shl and shr to simplify code. shl and shr could be replaced by functions.
|
|
|
|
new shift32 with carry module needed by the residue module.
|
|
|
|
|
|
|
|
|