Merge branch 'config_core_selector'

1 files changed, 123 insertions, 133 deletions

diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v
index 65f4058..ebda365 100644
--- a/src/rtl/modexp.v
+++ b/src/rtl/modexp.v
@@ -63,7 +63,7 @@ module modexp(
               input wire           cs,
               input wire           we,
 
-              input wire  [11 : 0] address,
+              input wire  [ 7 : 0] address,
               input wire  [31 : 0] write_data,
               output wire [31 : 0] read_data
              );
@@ -72,6 +72,7 @@ module modexp(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
+
   // The operand width is the internal operand width in bits.
   // The address width is the size of the address space used. This
   // value must be balances with OPERAND_WIDTH to allow a total
@@ -80,7 +81,6 @@ module modexp(
   localparam OPERAND_WIDTH         = 32;
   localparam ADDRESS_WIDTH         = 8;
 
-  localparam GENERAL_PREFIX        = 4'h0;
   localparam ADDR_NAME0            = 8'h00;
   localparam ADDR_NAME1            = 8'h01;
   localparam ADDR_VERSION          = 8'h02;
@@ -269,138 +269,128 @@ module modexp(
 
       if (cs)
         begin
-          case (address[11 : 8])
-            GENERAL_PREFIX:
-              begin
-                if (we)
-                  begin
-                    case (address[7 : 0])
-                      ADDR_CTRL:
-                        begin
-                          start_new = write_data[0];
-                        end
-
-                      ADDR_MODULUS_LENGTH:
-                        begin
-                          modulus_length_we = 1'b1;
-                        end
-
-                      ADDR_EXPONENT_LENGTH:
-                        begin
-                          exponent_length_we = 1'b1;
-                        end
-
-                      ADDR_MODULUS_PTR_RST:
-                        begin
-                          modulus_mem_api_rst = 1'b1;
-                        end
-
-                      ADDR_MODULUS_DATA:
-                        begin
-                          modulus_mem_api_cs = 1'b1;
-                          modulus_mem_api_wr = 1'b1;
-                        end
-
-                      ADDR_EXPONENT_PTR_RST:
-                        begin
-                          exponent_mem_api_rst = 1'b1;
-                        end
-
-                      ADDR_EXPONENT_DATA:
-                        begin
-                          exponent_mem_api_cs = 1'b1;
-                          exponent_mem_api_wr = 1'b1;
-                        end
-
-                      ADDR_MESSAGE_PTR_RST:
-                        begin
-                          message_mem_api_rst = 1'b1;
-                        end
-
-                      ADDR_MESSAGE_DATA:
-                        begin
-                          message_mem_api_cs = 1'b1;
-                          message_mem_api_wr = 1'b1;
-                        end
-
-                      ADDR_RESULT_PTR_RST:
-                        begin
-                          result_mem_api_rst = 1'b1;
-                        end
-
-                      default:
-                        begin
-                        end
-                    endcase // case (address[7 : 0])
-                  end
-                else
-                  begin
-                    case (address[7 : 0])
-                      ADDR_NAME0:
-                        tmp_read_data = CORE_NAME0;
-
-                      ADDR_NAME1:
-                        tmp_read_data = CORE_NAME1;
-
-                      ADDR_VERSION:
-                        tmp_read_data = CORE_VERSION;
-
-                      ADDR_CTRL:
-                        tmp_read_data = {31'h00000000, start_reg};
-
-                      ADDR_STATUS:
-                        tmp_read_data = {31'h00000000, ready};
-
-                      ADDR_CYCLES_HIGH:
-                        tmp_read_data = cycles[63 : 32];
-
-                      ADDR_CYCLES_LOW:
-                        tmp_read_data = cycles[31 : 0];
-
-                      ADDR_MODULUS_LENGTH:
-                        tmp_read_data = {24'h000000, modulus_length_reg};
-
-                      ADDR_EXPONENT_LENGTH:
-                        tmp_read_data = {24'h000000, exponent_length_reg};
-
-                      ADDR_MODULUS_DATA:
-                        begin
-                          modulus_mem_api_cs = 1'b1;
-                          tmp_read_data      = modulus_mem_api_read_data;
-                        end
-
-                      ADDR_EXPONENT_DATA:
-                        begin
-                          exponent_mem_api_cs = 1'b1;
-                          tmp_read_data       = exponent_mem_api_read_data;
-                        end
-
-                      ADDR_MESSAGE_DATA:
-                        begin
-                          message_mem_api_cs = 1'b1;
-                          tmp_read_data      = message_mem_api_read_data;
-                        end
-
-                      ADDR_RESULT_DATA:
-                        begin
-                          result_mem_api_cs = 1'b1;
-                          tmp_read_data     = result_mem_api_read_data;
-                        end
-
-                      default:
-                        begin
-                        end
-                    endcase // case (address[7 : 0])
-                  end
-              end
-
-            default:
-              begin
-
-              end
-          endcase // case (address[11 : 8])
+           if (we)
+             begin
+                case (address)
+                  ADDR_CTRL:
+                    begin
+                       start_new = write_data[0];
+                    end
+
+                  ADDR_MODULUS_LENGTH:
+                    begin
+                       modulus_length_we = 1'b1;
+                    end
+
+                  ADDR_EXPONENT_LENGTH:
+                    begin
+                       exponent_length_we = 1'b1;
+                    end
+
+                  ADDR_MODULUS_PTR_RST:
+                    begin
+                       modulus_mem_api_rst = 1'b1;
+                    end
+
+                  ADDR_MODULUS_DATA:
+                    begin
+                       modulus_mem_api_cs = 1'b1;
+                       modulus_mem_api_wr = 1'b1;
+                    end
+
+                  ADDR_EXPONENT_PTR_RST:
+                    begin
+                       exponent_mem_api_rst = 1'b1;
+                    end
+
+                  ADDR_EXPONENT_DATA:
+                    begin
+                       exponent_mem_api_cs = 1'b1;
+                       exponent_mem_api_wr = 1'b1;
+                    end
+
+                  ADDR_MESSAGE_PTR_RST:
+                    begin
+                       message_mem_api_rst = 1'b1;
+                    end
+
+                  ADDR_MESSAGE_DATA:
+                    begin
+                       message_mem_api_cs = 1'b1;
+                       message_mem_api_wr = 1'b1;
+                    end
+
+                  ADDR_RESULT_PTR_RST:
+                    begin
+                       result_mem_api_rst = 1'b1;
+                    end
+
+                  default:
+                    begin
+                    end
+                endcase // case (address[7 : 0])
+             end // if (we)
+           else
+             begin
+                case (address)
+                  ADDR_NAME0:
+                    tmp_read_data = CORE_NAME0;
+
+                  ADDR_NAME1:
+                    tmp_read_data = CORE_NAME1;
+
+                  ADDR_VERSION:
+                    tmp_read_data = CORE_VERSION;
+
+                  ADDR_CTRL:
+                    tmp_read_data = {31'h00000000, start_reg};
+
+                  ADDR_STATUS:
+                    tmp_read_data = {31'h00000000, ready};
+
+                  ADDR_CYCLES_HIGH:
+                    tmp_read_data = cycles[63 : 32];
+
+                  ADDR_CYCLES_LOW:
+                    tmp_read_data = cycles[31 : 0];
+
+                  ADDR_MODULUS_LENGTH:
+                    tmp_read_data = {24'h000000, modulus_length_reg};
+
+                  ADDR_EXPONENT_LENGTH:
+                    tmp_read_data = {24'h000000, exponent_length_reg};
+
+                  ADDR_MODULUS_DATA:
+                    begin
+                       modulus_mem_api_cs = 1'b1;
+                       tmp_read_data      = modulus_mem_api_read_data;
+                    end
+
+                  ADDR_EXPONENT_DATA:
+                    begin
+                       exponent_mem_api_cs = 1'b1;
+                       tmp_read_data       = exponent_mem_api_read_data;
+                    end
+
+                  ADDR_MESSAGE_DATA:
+                    begin
+                       message_mem_api_cs = 1'b1;
+                       tmp_read_data      = message_mem_api_read_data;
+                    end
+
+                  ADDR_RESULT_DATA:
+                    begin
+                       result_mem_api_cs = 1'b1;
+                       tmp_read_data     = result_mem_api_read_data;
+                    end
+
+                  default:
+                    begin
+                    end
+                endcase // case (address)
+             end // else: !if(we)
         end // if (cs)
-    end // api
+    end // block: api
 
 endmodule // modexp