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-rw-r--r--src/rtl/modexp_core.v14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/rtl/modexp_core.v b/src/rtl/modexp_core.v
index 45d1aa9..c1a88d1 100644
--- a/src/rtl/modexp_core.v
+++ b/src/rtl/modexp_core.v
@@ -236,7 +236,8 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
reg residue_valid_new;
reg residue_valid_int_validated;
- wire [7 : 0] length_m1;
+ wire [7 : 0] modulus_length_m1;
+ wire [7 : 0] exponent_length_m1;
//----------------------------------------------------------------
@@ -245,7 +246,8 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
assign ready = ready_reg;
assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg};
- assign length_m1 = modulus_length - 8'h1;
+ assign modulus_length_m1 = modulus_length - 8'h1;
+ assign exponent_length_m1 = exponent_length - 8'h1;
//----------------------------------------------------------------
@@ -495,10 +497,10 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
one_new = 32'h00000000;
b_one_new = 32'h00000000;
- if (montprod_opa_addr == length_m1)
+ if (montprod_opa_addr == modulus_length_m1)
one_new = 32'h00000001;
- if (montprod_opb_addr == length_m1)
+ if (montprod_opb_addr == modulus_length_m1)
b_one_new = 32'h00000001;
end
@@ -644,7 +646,7 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
loop_counter_new = 13'b0;
loop_counter_we = 1'b0;
- if (loop_counter_reg == {length_m1, 5'b11111})
+ if (loop_counter_reg == {exponent_length_m1, 5'b11111})
last_iteration = 1'b1;
else
last_iteration = 1'b0;
@@ -678,7 +680,7 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
begin : exponent_process
// Accessing new instead of reg - pick up update at
// CTRL_ITERATE_NEW to remove a pipeline stall.
- E_word_index = length_m1 - loop_counter_new[ 12 : 5 ];
+ E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ];
E_bit_index = loop_counter_reg[ 04 : 0 ];