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-rw-r--r--src/rtl/blockmem2r1wptr.v44
-rw-r--r--src/rtl/blockmem2rptr1w.v41
-rw-r--r--src/rtl/modexp_core.v239
-rw-r--r--src/rtl/montprod.v6
4 files changed, 175 insertions, 155 deletions
diff --git a/src/rtl/blockmem2r1wptr.v b/src/rtl/blockmem2r1wptr.v
index 41efc85..b9abfa8 100644
--- a/src/rtl/blockmem2r1wptr.v
+++ b/src/rtl/blockmem2r1wptr.v
@@ -8,6 +8,12 @@
// when the cs signal is set. The pointer is reset to zero when
// the rst signal is asserted.
//
+//
+// NOTE: This memory needs to be rebuilt if interface 0 is changed
+// to use bigger operand widths and fewer words than interface 1.
+// This adaption is NOT automatic.
+//
+//
// The memory is used in the modexp core.
//
//
@@ -42,32 +48,32 @@
//
//======================================================================
-module blockmem2r1wptr(
- input wire clk,
- input wire reset_n,
-
- input wire [07 : 0] read_addr0,
- output wire [31 : 0] read_data0,
+module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
+ input wire reset_n,
- output wire [31 : 0] read_data1,
+ input wire [(ADW - 1) : 0] read_addr0,
+ output wire [(OPW - 1) : 0] read_data0,
- input wire rst,
- input wire cs,
- input wire wr,
- input wire [31 : 0] write_data
+ output wire [31 : 0] read_data1,
+ input wire rst,
+ input wire cs,
+ input wire wr,
+ input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data0;
- reg [31 : 0] tmp_read_data1;
+ reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data0;
+ reg [31 : 0] tmp_read_data1;
- reg [7 : 0] ptr_reg;
- reg [7 : 0] ptr_new;
- reg ptr_we;
+ reg [7 : 0] ptr_reg;
+ reg [7 : 0] ptr_new;
+ reg ptr_we;
//----------------------------------------------------------------
@@ -94,10 +100,10 @@ module blockmem2r1wptr(
//----------------------------------------------------------------
- // reg_update
+ // ptr_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
- begin : reg_mem_update
+ begin : ptr_update
if (!reset_n)
ptr_reg <= 8'h00;
diff --git a/src/rtl/blockmem2rptr1w.v b/src/rtl/blockmem2rptr1w.v
index 4eb529e..fc7d83a 100644
--- a/src/rtl/blockmem2rptr1w.v
+++ b/src/rtl/blockmem2rptr1w.v
@@ -9,6 +9,11 @@
// The memory is used in the modexp core.
//
//
+// NOTE: This memory needs to be rebuilt if interface 0 is changed
+// to use bigger operand widths and fewer words than interface 1.
+// This adaption is NOT automatic.
+//
+//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
@@ -40,33 +45,33 @@
//
//======================================================================
-module blockmem2rptr1w(
- input wire clk,
- input wire reset_n,
-
- input wire [07 : 0] read_addr0,
- output wire [31 : 0] read_data0,
+module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
+ input wire reset_n,
- output wire [31 : 0] read_data1,
+ input wire [(ADW - 1) : 0] read_addr0,
+ output wire [(OPW - 1) : 0] read_data0,
- input wire rst,
- input wire cs,
- input wire wr,
- input wire [07 : 0] write_addr,
- input wire [31 : 0] write_data
+ output wire [31 : 0] read_data1,
+ input wire rst,
+ input wire cs,
+ input wire wr,
+ input wire [07 : 0] write_addr,
+ input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data0;
- reg [31 : 0] tmp_read_data1;
+ reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data0;
+ reg [31 : 0] tmp_read_data1;
- reg [7 : 0] ptr_reg;
- reg [7 : 0] ptr_new;
- reg ptr_we;
+ reg [7 : 0] ptr_reg;
+ reg [7 : 0] ptr_new;
+ reg ptr_we;
//----------------------------------------------------------------
diff --git a/src/rtl/modexp_core.v b/src/rtl/modexp_core.v
index aa8a758..45d1aa9 100644
--- a/src/rtl/modexp_core.v
+++ b/src/rtl/modexp_core.v
@@ -251,121 +251,130 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
- montprod montprod_inst(
- .clk(clk),
- .reset_n(reset_n),
-
- .calculate(montprod_calc),
- .ready(montprod_ready),
-
- .length(montprod_length),
-
- .opa_addr(montprod_opa_addr),
- .opa_data(montprod_opa_data),
-
- .opb_addr(montprod_opb_addr),
- .opb_data(montprod_opb_data),
-
- .opm_addr(montprod_opm_addr),
- .opm_data(montprod_opm_data),
-
- .result_addr(montprod_result_addr),
- .result_data(montprod_result_data),
- .result_we(montprod_result_we)
- );
-
-
- residue residue_inst(
- .clk(clk),
- .reset_n(reset_n),
- .calculate(residue_calculate),
- .ready(residue_ready),
- .nn(residue_nn),
- .length(residue_length),
- .opa_rd_addr(residue_opa_rd_addr),
- .opa_rd_data(residue_opa_rd_data),
- .opa_wr_addr(residue_opa_wr_addr),
- .opa_wr_data(residue_opa_wr_data),
- .opa_wr_we(residue_opa_wr_we),
- .opm_addr(residue_opm_addr),
- .opm_data(residue_opm_data)
- );
-
- blockmem2r1w residue_mem(
- .clk(clk),
- .read_addr0(residue_opa_rd_addr),
- .read_data0(residue_opa_rd_data),
- .read_addr1(residue_mem_montprod_read_addr),
- .read_data1(residue_mem_montprod_read_data),
- .wr(residue_opa_wr_we),
- .write_addr(residue_opa_wr_addr),
- .write_data(residue_opa_wr_data)
- );
-
-
- blockmem2r1w p_mem(
- .clk(clk),
- .read_addr0(p_mem_rd0_addr),
- .read_data0(p_mem_rd0_data),
- .read_addr1(p_mem_rd1_addr),
- .read_data1(p_mem_rd1_data),
- .wr(p_mem_we),
- .write_addr(p_mem_wr_addr),
- .write_data(p_mem_wr_data)
- );
-
-
- blockmem2r1wptr exponent_mem(
- .clk(clk),
- .reset_n(reset_n),
- .read_addr0(exponent_mem_int_rd_addr),
- .read_data0(exponent_mem_int_rd_data),
- .read_data1(exponent_mem_api_read_data),
- .rst(exponent_mem_api_rst),
- .cs(exponent_mem_api_cs),
- .wr(exponent_mem_api_wr),
- .write_data(exponent_mem_api_write_data)
- );
-
-
- blockmem2r1wptr modulus_mem(
- .clk(clk),
- .reset_n(reset_n),
- .read_addr0(modulus_mem_int_rd_addr),
- .read_data0(modulus_mem_int_rd_data),
- .read_data1(modulus_mem_api_read_data),
- .rst(modulus_mem_api_rst),
- .cs(modulus_mem_api_cs),
- .wr(modulus_mem_api_wr),
- .write_data(modulus_mem_api_write_data)
- );
-
-
- blockmem2r1wptr message_mem(
- .clk(clk),
- .reset_n(reset_n),
- .read_addr0(message_mem_int_rd_addr),
- .read_data0(message_mem_int_rd_data),
- .read_data1(message_mem_api_read_data),
- .rst(message_mem_api_rst),
- .cs(message_mem_api_cs),
- .wr(message_mem_api_wr),
- .write_data(message_mem_api_write_data)
- );
-
-
- blockmem2rptr1w result_mem(
- .clk(clk),
- .reset_n(reset_n),
- .read_addr0(result_mem_int_rd_addr[7 : 0]),
- .read_data0(result_mem_int_rd_data),
- .read_data1(result_mem_api_read_data),
- .rst(result_mem_api_rst),
- .cs(result_mem_api_cs),
- .wr(result_mem_int_we),
- .write_addr(result_mem_int_wr_addr),
- .write_data(result_mem_int_wr_data)
- );
+ montprod #(.OPW(OPW), .ADW(ADW))
+ montprod_inst(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .calculate(montprod_calc),
+ .ready(montprod_ready),
+
+ .length(montprod_length),
+
+ .opa_addr(montprod_opa_addr),
+ .opa_data(montprod_opa_data),
+
+ .opb_addr(montprod_opb_addr),
+ .opb_data(montprod_opb_data),
+
+ .opm_addr(montprod_opm_addr),
+ .opm_data(montprod_opm_data),
+
+ .result_addr(montprod_result_addr),
+ .result_data(montprod_result_data),
+ .result_we(montprod_result_we)
+ );
+
+
+ residue #(.OPW(OPW), .ADW(ADW))
+ residue_inst(
+ .clk(clk),
+ .reset_n(reset_n),
+ .calculate(residue_calculate),
+ .ready(residue_ready),
+ .nn(residue_nn),
+ .length(residue_length),
+ .opa_rd_addr(residue_opa_rd_addr),
+ .opa_rd_data(residue_opa_rd_data),
+ .opa_wr_addr(residue_opa_wr_addr),
+ .opa_wr_data(residue_opa_wr_data),
+ .opa_wr_we(residue_opa_wr_we),
+ .opm_addr(residue_opm_addr),
+ .opm_data(residue_opm_data)
+ );
+
+
+ blockmem2r1w #(.OPW(OPW), .ADW(ADW))
+ residue_mem(
+ .clk(clk),
+ .read_addr0(residue_opa_rd_addr),
+ .read_data0(residue_opa_rd_data),
+ .read_addr1(residue_mem_montprod_read_addr),
+ .read_data1(residue_mem_montprod_read_data),
+ .wr(residue_opa_wr_we),
+ .write_addr(residue_opa_wr_addr),
+ .write_data(residue_opa_wr_data)
+ );
+
+
+ blockmem2r1w #(.OPW(OPW), .ADW(ADW))
+ p_mem(
+ .clk(clk),
+ .read_addr0(p_mem_rd0_addr),
+ .read_data0(p_mem_rd0_data),
+ .read_addr1(p_mem_rd1_addr),
+ .read_data1(p_mem_rd1_data),
+ .wr(p_mem_we),
+ .write_addr(p_mem_wr_addr),
+ .write_data(p_mem_wr_data)
+ );
+
+
+ blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
+ exponent_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(exponent_mem_int_rd_addr),
+ .read_data0(exponent_mem_int_rd_data),
+ .read_data1(exponent_mem_api_read_data),
+ .rst(exponent_mem_api_rst),
+ .cs(exponent_mem_api_cs),
+ .wr(exponent_mem_api_wr),
+ .write_data(exponent_mem_api_write_data)
+ );
+
+
+ blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
+ modulus_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(modulus_mem_int_rd_addr),
+ .read_data0(modulus_mem_int_rd_data),
+ .read_data1(modulus_mem_api_read_data),
+ .rst(modulus_mem_api_rst),
+ .cs(modulus_mem_api_cs),
+ .wr(modulus_mem_api_wr),
+ .write_data(modulus_mem_api_write_data)
+ );
+
+
+ blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
+ message_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(message_mem_int_rd_addr),
+ .read_data0(message_mem_int_rd_data),
+ .read_data1(message_mem_api_read_data),
+ .rst(message_mem_api_rst),
+ .cs(message_mem_api_cs),
+ .wr(message_mem_api_wr),
+ .write_data(message_mem_api_write_data)
+ );
+
+
+ blockmem2rptr1w #(.OPW(OPW), .ADW(ADW))
+ result_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(result_mem_int_rd_addr[7 : 0]),
+ .read_data0(result_mem_int_rd_data),
+ .read_data1(result_mem_api_read_data),
+ .rst(result_mem_api_rst),
+ .cs(result_mem_api_cs),
+ .wr(result_mem_int_we),
+ .write_addr(result_mem_int_wr_addr),
+ .write_data(result_mem_int_wr_data)
+ );
//----------------------------------------------------------------
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index c50751b..fa7c438 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -126,9 +126,9 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
reg [(ADW - 1) : 0] b_word_index; //loop counter as a word index
- reg [04 : 0] b_bit_index_reg;
- reg [04 : 0] b_bit_index_new;
- reg b_bit_index_we;
+ reg [(13 - ADW - 1) : 0] b_bit_index_reg;
+ reg [(13 - ADW - 1) : 0] b_bit_index_new;
+ reg b_bit_index_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 18:10:48 +0000