diff options
Diffstat (limited to 'src/rtl/modexp_core.v')
| -rw-r--r-- | src/rtl/modexp_core.v | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/rtl/modexp_core.v b/src/rtl/modexp_core.v index b8c4403..6dd1570 100644 --- a/src/rtl/modexp_core.v +++ b/src/rtl/modexp_core.v @@ -236,6 +236,8 @@ module modexp_core( reg residue_valid_int_validated; wire [7 : 0] length_m1; + wire [7 : 0] modulus_length_m1; + wire [7 : 0] exponent_length_m1; //---------------------------------------------------------------- @@ -244,7 +246,9 @@ module modexp_core( assign ready = ready_reg; assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg}; - assign length_m1 = modulus_length - 8'h1; + + assign modulus_length_m1 = modulus_length - 8'h1; + assign exponent_length_m1 = exponent_length - 8'h1; //---------------------------------------------------------------- @@ -485,10 +489,10 @@ module modexp_core( one_new = 32'h00000000; b_one_new = 32'h00000000; - if (montprod_opa_addr == length_m1) + if (montprod_opa_addr == modulus_length_m1) one_new = 32'h00000001; - if (montprod_opb_addr == length_m1) + if (montprod_opb_addr == modulus_length_m1) b_one_new = 32'h00000001; end @@ -634,7 +638,7 @@ module modexp_core( loop_counter_new = 13'b0; loop_counter_we = 1'b0; - if (loop_counter_reg == {length_m1, 5'b11111}) + if (loop_counter_reg == {exponent_length_m1, 5'b11111}) last_iteration = 1'b1; else last_iteration = 1'b0; @@ -668,7 +672,7 @@ module modexp_core( begin : exponent_process // Accessing new instead of reg - pick up update at // CTRL_ITERATE_NEW to remove a pipeline stall. - E_word_index = length_m1 - loop_counter_new[ 12 : 5 ]; + E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ]; E_bit_index = loop_counter_reg[ 04 : 0 ]; |