diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-04-27 11:17:08 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-04-27 11:17:08 +0200 |
| commit | a315223f98fa6f1fdea2b1080c5f3e33352ebb13 (patch) | |
| tree | 0fb3f6c458df78f58017e9475ff3b0c5cb3b52d0 /src/tb/tb_montprod.v | |
| parent | 502f0f429a261628fe5e43582280012541c40804 (diff) | |
Updating modexp core to v 0.50. This version contains a working core that can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
Diffstat (limited to 'src/tb/tb_montprod.v')
| -rw-r--r-- | src/tb/tb_montprod.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/tb/tb_montprod.v b/src/tb/tb_montprod.v index 59ec72e..601e7f8 100644 --- a/src/tb/tb_montprod.v +++ b/src/tb/tb_montprod.v @@ -220,7 +220,7 @@ task reset_dut(); begin $display("*** Toggle reset."); tb_reset_n = 0; - #(4 * CLK_HALF_PERIOD); + #(2 * CLK_PERIOD); tb_reset_n = 1; end endtask // reset_dut @@ -260,7 +260,7 @@ task wait_ready(); integer i; for (i=0; i<1000000; i=i+1) if (tb_ready == 0) - #(2 * CLK_HALF_PERIOD); + #(CLK_PERIOD); end if (tb_ready == 0) begin @@ -276,7 +276,7 @@ task signal_calculate(); begin $display("*** signal_calculate"); tb_calculate = 1; - #(2 * CLK_HALF_PERIOD); + #(CLK_PERIOD); tb_calculate = 0; end endtask // signal_calculate |