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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-22 11:55:36 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-22 11:55:36 +0200
commit244a915df114cefd75fcf0564a89b79eca7f3756 (patch)
tree01076dc422276638b2299142517c34cb5f071d21 /src/rtl
parentbba9af35a9ed26870d7fcf16749cfcf7e6b38618 (diff)
Cleanup of prodcalc.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/montprod.v62
1 files changed, 27 insertions, 35 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 00227d0..6d3d865 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -291,34 +291,25 @@ module montprod(
//----------------------------------------------------------------
always @*
begin : prodcalc
- opb_addr_reg = b_word_index;
- opm_addr_reg = word_index_reg;
+ opa_addr_reg = word_index_reg;
+ opb_addr_reg = b_word_index;
+ opm_addr_reg = word_index_reg;
+ s_mem_addr = word_index_reg;
+ tmp_result_we = 1'b0;
+
result_addr_reg = word_index_prev_reg;
result_data_reg = s_mem_read_data;
- case (montprod_ctrl_reg)
- CTRL_LOOP_ITER:
- //q = (s[length-1] ^ A[length-1]) & 1;
- opa_addr_reg = length_m1;
- default:
- opa_addr_reg = word_index_reg;
- endcase
+ if (montprod_ctrl_reg == CTRL_LOOP_ITER)
+ opa_addr_reg = length_m1;
- case (montprod_ctrl_reg)
- CTRL_LOOP_ITER:
+ if (montprod_ctrl_reg == CTRL_LOOP_ITER)
s_mem_addr = length_m1;
- default:
- s_mem_addr = word_index_reg;
- endcase
- case (montprod_ctrl_reg)
- CTRL_EMIT_S:
- tmp_result_we = 1'b1;
- default:
- tmp_result_we = 1'b0;
- endcase
+ if (montprod_ctrl_reg == CTRL_EMIT_S)
+ tmp_result_we = 1'b1;
if (reset_word_index_lsw == 1'b1)
@@ -336,14 +327,18 @@ module montprod(
//----------------------------------------------------------------
- // s_select_write
+ // s_logic
//----------------------------------------------------------------
always @*
- begin : s_select_write
+ begin : s_logic
shr_carry_in_new = 1'b0;
muxed_s_mem_read_data = 32'h0;
- s_mem_we_new = 1'b0;
sa_adder_data_in = 32'h0;
+ add_carry_in_sa_new = 1'b0;
+ add_carry_in_sm_new = 1'b0;
+ s_mem_new = 32'h0;
+ s_mem_we_new = 1'b0;
+
case (montprod_ctrl_reg)
CTRL_INIT_S:
@@ -368,9 +363,6 @@ module montprod(
end
endcase
- s_mem_new = 32'h0;
- add_carry_in_sa_new = 1'b0;
- add_carry_in_sm_new = 1'b0;
case (s_mux_reg)
SMUX_0:
@@ -412,7 +404,7 @@ module montprod(
begin
end
endcase
- end // block: s_writer
+ end // s_logic
//----------------------------------------------------------------
@@ -483,11 +475,11 @@ module montprod(
begin
if (calculate)
begin
- ready_new = 1'b0;
- ready_we = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ first_iteration_new = 1'b0;
+ first_iteration_we = 1'b1;
reset_word_index_lsw = 1'b1;
-// first_iteration_new = 1'b1;
-// first_iteration_we = 1'b1;
montprod_ctrl_new = CTRL_INIT_S;
montprod_ctrl_we = 1'b1;
end
@@ -499,7 +491,6 @@ module montprod(
if (word_index_reg == 8'h0)
begin
- loop_ctr_set = 1'b1;
montprod_ctrl_new = CTRL_WAIT;
montprod_ctrl_we = 1'b1;
end
@@ -507,6 +498,7 @@ module montprod(
CTRL_WAIT:
begin
+ loop_ctr_set = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
end
@@ -531,7 +523,7 @@ module montprod(
CTRL_L_CALC_SA:
begin
- s_mux_new = SMUX_ADD_SA;
+ s_mux_new = SMUX_ADD_SA;
if (word_index_reg == 8'h0)
begin
@@ -543,8 +535,8 @@ module montprod(
CTRL_L_STALLPIPE_SA:
begin
-// first_iteration_new = 1'b0;
-// first_iteration_we = 1'b1;
+ first_iteration_new = 1'b0;
+ first_iteration_we = 1'b1;
montprod_ctrl_new = CTRL_L_CALC_SDIV2;
montprod_ctrl_we = 1'b1;
reset_word_index_msw = 1'b1;