(1) Modexp with better API. (2) Adding working residue module. (3) Adding new shift32 with carry module needed by the residue module.

1 files changed, 66 insertions, 89 deletions

diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v
index b0e8aa3..8721ce9 100644
--- a/src/rtl/modexp.v
+++ b/src/rtl/modexp.v
@@ -17,10 +17,10 @@
 //
 // The core has a 32-bit memory like interface, but provides
 // status signals to inform the system that a given operation
-// has is done. Additionally, any errors will also be asserted.
+// has completed. Additionally, any errors will also be asserted.
 //
 //
-// Author: Peter Magnusson, Joachim Strombergson
+// Author: Joachim Strombergson, Peter Magnusson
 // Copyright (c) 2015, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -72,8 +72,15 @@ module modexp(
   localparam ADDR_NAME1          = 8'h01;
   localparam ADDR_VERSION        = 8'h02;
 
-  localparam ADDR_MODSIZE        = 8'h10;
-  localparam ADDR_EXPONENT       = 8'h20;
+  localparam ADDR_CTRL           = 8'h00;
+  localparam CTRL_INIT_BIT       = 0;
+  localparam CTRL_NEXT_BIT       = 1;
+
+  localparam ADDR_STATUS         = 8'h09;
+
+  localparam ADDR_MODSIZE        = 8'h20;
+  localparam ADDR_LENGTH         = 8'h21;
+  localparam ADDR_EXPONENT       = 8'h22;
 
   localparam MODULUS_PREFIX      = 4'h1;
   localparam ADDR_MODULUS_START  = 8'h00;
@@ -117,8 +124,8 @@ module modexp(
   localparam CTRL_CALCULATE_ZN   = 4'h8;
   localparam CTRL_DONE           = 4'h9;
 
-  localparam CORE_NAME0          = 32'h72736120; // "rsa "
-  localparam CORE_NAME1          = 32'h38313932; // "8192"
+  localparam CORE_NAME0          = 32'h6d6f6465; // "mode"
+  localparam CORE_NAME1          = 32'h78702020; // "xp  "
   localparam CORE_VERSION        = 32'h302e3031; // "0.01"
 
 
@@ -309,15 +316,15 @@ module modexp(
                          );
 
   blockmem2r1w p_mem(
-                           .clk(clk),
-                           .read_addr0(p_mem_rd0_addr),
-                           .read_data0(p_mem_rd0_data),
-                           .read_addr1(p_mem_rd1_addr),
-                           .read_data1(p_mem_rd1_data),
-                           .wr(p_mem_we),
-                           .write_addr(p_mem_wr_addr),
-                           .write_data(p_mem_wr_data)
-                           );
+                     .clk(clk),
+                     .read_addr0(p_mem_rd0_addr),
+                     .read_data0(p_mem_rd0_data),
+                     .read_addr1(p_mem_rd1_addr),
+                     .read_data1(p_mem_rd1_data),
+                     .wr(p_mem_we),
+                     .write_addr(p_mem_wr_addr),
+                     .write_data(p_mem_wr_data)
+                    );
 
 
   //----------------------------------------------------------------
@@ -357,8 +364,8 @@ module modexp(
 
           if (length_we)
             begin
-              length_reg <= length_new;
-              length_m1_reg <= length_m1_new;
+              length_reg    <= write_data[7 : 0];
+              length_m1_reg <= write_data[7 : 0] - 8'h1;
             end
 
           if (loop_counter_we)
@@ -382,67 +389,51 @@ module modexp(
       modulus_mem_api_we  = 1'b0;
       exponent_mem_api_we = 1'b0;
       message_mem_api_we  = 1'b0;
+      length_we           = 1'b0;
       tmp_read_data       = 32'h00000000;
 
-      length_new = write_data[7 : 0];
-      length_m1_new = write_data[7 : 0] - 8'h1;
-      length_we = 1'b0;
-
       if (cs)
         begin
           case (address[11 : 8])
             GENERAL_PREFIX:
               begin
-//                if (we)
-//                  begin
-//                    case (address)
-//                      // Write operations.
-//                      ADDR_MODSIZE:
-//                        begin
-//                          modsize_we  = 1;
-//                        end
-//
-//                      ADDR_EXPONENT:
-//                        begin
-//                          exponent_we = 1;
-//                        end
-//
-//                      default:
-//                        begin
-//                          tmp_error = 1;
-//                        end
-//                    endcase // case (addr)
-//                  end // if (write_read)
-//                else
-//                  begin
-//                    case (address)
-//                      // Read operations.
-//                      ADDR_NAME0:
-//                        begin
-//                          tmp_read_data = CORE_NAME0;
-//                        end
-//
-//                      ADDR_NAME1:
-//                        begin
-//                          tmp_read_data = CORE_NAME1;
-//                        end
-//
-//                      ADDR_VERSION:
-//                        begin
-//                          tmp_read_data = CORE_VERSION;
-//                        end
-//
-//                      ADDR_MODSIZE:
-//                        begin
-//                          tmp_read_data = {28'h0000000, modsize_reg};
-//                        end
-//
-//                      default:
-//                        begin
-//                          tmp_error = 1;
-//                        end
-//                    endcase // case (addr)
-//                  end
+                if (we)
+                  begin
+                    case (address[7 : 0])
+                      ADDR_LENGTH:
+                        length_we = 1'b1;
+
+                      default:
+                        begin
+                        end
+                    endcase // case (address[7 : 0])
+                  end
+                else
+                  begin
+                    case (address[7 : 0])
+                      ADDR_NAME0:
+                        tmp_read_data = CORE_NAME0;
+
+                      ADDR_NAME1:
+                        tmp_read_data = CORE_NAME1;
+
+                      ADDR_VERSION:
+                        tmp_read_data = CORE_VERSION;
+
+                      ADDR_CTRL:
+                        tmp_read_data = 32'h00000000;
+
+                      ADDR_STATUS:
+                        tmp_read_data = 32'h00000000;
+
+                      ADDR_LENGTH:
+                        tmp_read_data = {24'h000000, length_reg};
+
+                      default:
+                        begin
+                        end
+                    endcase // case (address[7 : 0])
+                  end
               end
 
             MODULUS_PREFIX:
@@ -486,24 +477,6 @@ module modexp(
                 tmp_read_data = result_mem_api_rd_data;
               end
 
-            LENGTH_PREFIX:
-              begin
-                if (we)
-                  length_we = 1'b1;
-              end
-
-//            RESULT_PREFIX:
-//              begin
-//                if (we)
-//                  begin
-//                    modulus_mem_api_we = 1'b1;
-//                  end
-//                else
-//                  begin
-//                    tmp_read_data = modulus_mem_int_rd_data;
-//                  end
-//              end
-
             default:
               begin
 
@@ -574,6 +547,7 @@ module modexp(
       endcase // case (montprod_selcect_reg)
     end
 
+
   //----------------------------------------------------------------
   // memory write mux
   //
@@ -604,6 +578,7 @@ module modexp(
         result_mem_int_we = result_mem_int_we & ei_reg;
     end
 
+
   //----------------------------------------------------------------
   // loop_counter
   //
@@ -640,6 +615,7 @@ module modexp(
       endcase
     end
 
+
   //----------------------------------------------------------------
   // exponent
   //
@@ -660,6 +636,7 @@ module modexp(
         ei_we = 1'b0;
     end
 
+
   //----------------------------------------------------------------
   // modexp_ctrl
   //