Updated all modules below modexp_core has been updated to have generic operand size. Updated module integrations in modexp_core to set the operand width and address width.

1 files changed, 23 insertions, 18 deletions

diff --git a/src/rtl/blockmem2rptr1w.v b/src/rtl/blockmem2rptr1w.v
index 4eb529e..fc7d83a 100644
--- a/src/rtl/blockmem2rptr1w.v
+++ b/src/rtl/blockmem2rptr1w.v
@@ -9,6 +9,11 @@
 // The memory is used in the modexp core.
 //
 //
+// NOTE: This memory needs to be rebuilt if interface 0 is changed
+// to use bigger operand widths and fewer words than interface 1.
+// This adaption is NOT automatic.
+//
+//
 // Author: Joachim Strombergson
 // Copyright (c) 2015, NORDUnet A/S All rights reserved.
 //
@@ -40,33 +45,33 @@
 //
 //======================================================================
 
-module blockmem2rptr1w(
-                       input wire           clk,
-                       input wire           reset_n,
-
-                       input wire  [07 : 0] read_addr0,
-                       output wire [31 : 0] read_data0,
+module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
+                      (
+                       input wire                  clk,
+                       input wire                  reset_n,
 
-                       output wire [31 : 0] read_data1,
+                       input wire  [(ADW - 1) : 0] read_addr0,
+                       output wire [(OPW - 1) : 0] read_data0,
 
-                       input wire           rst,
-                       input wire           cs,
-                       input wire           wr,
-                       input wire  [07 : 0] write_addr,
-                       input wire  [31 : 0] write_data
+                       output wire [31 : 0]        read_data1,
+                       input wire                  rst,
+                       input wire                  cs,
+                       input wire                  wr,
+                       input wire  [07 : 0]        write_addr,
+                       input wire  [31 : 0]        write_data
                       );
 
 
   //----------------------------------------------------------------
   // Memories and regs including update variables and write enable.
   //----------------------------------------------------------------
-  reg [31 : 0] mem [0 : 255];
-  reg [31 : 0] tmp_read_data0;
-  reg [31 : 0] tmp_read_data1;
+  reg [(OPW - 1) : 0] mem [0 :  (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] tmp_read_data0;
+  reg [31 : 0]        tmp_read_data1;
 
-  reg [7 : 0] ptr_reg;
-  reg [7 : 0] ptr_new;
-  reg         ptr_we;
+  reg [7 : 0]         ptr_reg;
+  reg [7 : 0]         ptr_new;
+  reg                 ptr_we;
 
 
   //----------------------------------------------------------------