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author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-30 16:15:30 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-30 16:15:30 +0200 |
commit | 06fa4cc16f62f156143949328da7f6ab578cb365 (patch) | |
tree | e5f20dca7676d35ca2fe917ca02a4afb0cbff1af /src/rtl/blockmem1r1w.v | |
parent | ad4531bc8853d4ca349bb9afa25049631c0abbde (diff) |
Fixed errors in block memories.debug_bigoperands
Diffstat (limited to 'src/rtl/blockmem1r1w.v')
-rw-r--r-- | src/rtl/blockmem1r1w.v | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v index 1d84369..6856e0a 100644 --- a/src/rtl/blockmem1r1w.v +++ b/src/rtl/blockmem1r1w.v @@ -7,6 +7,9 @@ // // The memory is used in the modexp core. // +// paremeter OPW is operand word width in bits. +// parameter ADW is address width in bits. +// // // Author: Joachim Strombergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. @@ -39,19 +42,20 @@ // //====================================================================== -module blockmem1r1w( - input wire clk, +module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8) + ( + input wire clk, - input wire [07 : 0] read_addr, - output wire [31 : 0] read_data, + input wire [(ADW - 1) : 0] read_addr, + output wire [(OPW - 1) : 0] read_data, - input wire wr, - input wire [07 : 0] write_addr, - input wire [31 : 0] write_data + input wire wr, + input wire [(ADW - 1) : 0] write_addr, + input wire [(OPW - 1) : 0] write_data ); - reg [31 : 0] mem [0 : 255]; - reg [31 : 0] tmp_read_data; + reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)]; + reg [(OPW - 1) : 0] tmp_read_data; assign read_data = tmp_read_data; |