diff options
author | Joachim Strömbergson <joachim@secworks.se> | 2015-06-23 08:25:24 +0200 |
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committer | Joachim Strömbergson <joachim@secworks.se> | 2015-06-23 08:25:24 +0200 |
commit | c8c13f792e73b0729d9c533ad3c7295657975dc4 (patch) | |
tree | 5ff626a6bca289201fce6d159468567927707276 /src/rtl/adder32.v | |
parent | 5a0a6f87f2f63f9f1044725db0cac212c63f1fd6 (diff) |
Made the adder and shifters words size generic. Updated the montprod and residue to use the generic adder and shifters.
Diffstat (limited to 'src/rtl/adder32.v')
-rw-r--r-- | src/rtl/adder32.v | 42 |
1 files changed, 26 insertions, 16 deletions
diff --git a/src/rtl/adder32.v b/src/rtl/adder32.v index d9cac45..fa8ed8c 100644 --- a/src/rtl/adder32.v +++ b/src/rtl/adder32.v @@ -1,11 +1,12 @@ //====================================================================== // -// adder32.v -// --------- -// 32bit adder with carry in / carry out +// adder.v +// ------- +// Adder with separate carry in and carry out. Used in the montprod +// amd residue modules of the modexp core. // // -// Author: Peter Magnusson +// Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -36,19 +37,28 @@ // //====================================================================== +module adder #(parameter OPW = 32) + ( + input [(OPW - 1) : 0] a, + input [(OPW - 1) : 0] b, + input carry_in, -module adder32( - input [31 : 0] a, - input [31 : 0] b, - input carry_in, - output wire [31 : 0] sum, - output wire carry_out); + output wire [(OPW - 1) : 0] sum, + output wire carry_out + ); - reg [32 : 0] adder_result; + reg [(OPW) : 0] adder_result; - assign sum = adder_result[31:0]; - assign carry_out = adder_result[32]; + assign sum = adder_result[(OPW - 1) : 0]; + assign carry_out = adder_result[(OPW)]; - always @(a, b, carry_in) - adder_result = {1'b0, a} + {1'b0, b} + {32'b0, carry_in}; -endmodule + always @* + begin + adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in}; + end + +endmodule // adder + +//====================================================================== +// EOF adder.v +//====================================================================== |