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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-24 15:16:23 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-24 15:16:23 +0200
commit502f0f429a261628fe5e43582280012541c40804 (patch)
treea53cf2bac9474091157c4df56e75a333b3376e26 /src/model/java
parent7a6c9b5eb5a3d27be80c68eab583bd05e45bd310 (diff)
(1) Adding auto generated testbench for verilog. (2) Update of the test generator. (3) Update of the Makefile to run test generator.
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