diff options
Diffstat (limited to 'rtl/lowlevel/artix7/adder47_artix7.v')
-rw-r--r-- | rtl/lowlevel/artix7/adder47_artix7.v | 108 |
1 files changed, 54 insertions, 54 deletions
diff --git a/rtl/lowlevel/artix7/adder47_artix7.v b/rtl/lowlevel/artix7/adder47_artix7.v index 00566e4..caafc85 100644 --- a/rtl/lowlevel/artix7/adder47_artix7.v +++ b/rtl/lowlevel/artix7/adder47_artix7.v @@ -2,7 +2,7 @@ // // adder47_artix7.v // ----------------------------------------------------------------------------- -// Hardware (Artix-7 DSP48E1) 47-bit adder.
+// Hardware (Artix-7 DSP48E1) 47-bit adder. // // Authors: Pavel Shatov // @@ -34,58 +34,58 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -//------------------------------------------------------------------------------
-
-module adder47_artix7
- (
- input clk, // clock
- input [46: 0] a, // operand input
- input [46: 0] b, // operand input
- output [46: 0] s // sum output
- );
-
- //
- // Lower and higher parts of operand
- //
- wire [17: 0] bl = b[17: 0];
- wire [28: 0] bh = b[46:18];
-
- //
- // DSP48E1 Slice
- //
-
- /* Operation Mode */
- wire [ 3: 0] dsp48e1_alumode = 4'b0000;
- wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
-
- /* Internal Product */
- wire [47: 0] p_int;
-
- dsp48e1_wrapper dsp_adder
- (
- .clk (clk),
-
- .ce (1'b1),
-
- .carry (1'b0),
-
- .alumode (dsp48e1_alumode),
- .opmode (dsp48e1_opmode),
-
- .a ({1'b0, bh}),
- .b (bl),
- .c ({1'b0, a}),
-
- .p (p_int)
- );
-
- //
- // Output Mapping
- //
- assign s = p_int[46: 0];
-
-endmodule
-
+//------------------------------------------------------------------------------ + +module adder47_artix7 + ( + input clk, // clock + input [46: 0] a, // operand input + input [46: 0] b, // operand input + output [46: 0] s // sum output + ); + + // + // Lower and higher parts of operand + // + wire [17: 0] bl = b[17: 0]; + wire [28: 0] bh = b[46:18]; + + // + // DSP48E1 Slice + // + + /* Operation Mode */ + wire [ 3: 0] dsp48e1_alumode = 4'b0000; + wire [ 6: 0] dsp48e1_opmode = 7'b0110011; + + /* Internal Product */ + wire [47: 0] p_int; + + dsp48e1_wrapper dsp_adder + ( + .clk (clk), + + .ce (1'b1), + + .carry (1'b0), + + .alumode (dsp48e1_alumode), + .opmode (dsp48e1_opmode), + + .a ({1'b0, bh}), + .b (bl), + .c ({1'b0, a}), + + .p (p_int) + ); + + // + // Output Mapping + // + assign s = p_int[46: 0]; + +endmodule + //------------------------------------------------------------------------------ // End-of-File -//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------ |