diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-17 14:46:33 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-17 14:46:33 +0300 |
commit | 628d1dc860eb236fddbf5bb5e400bd74817cc317 (patch) | |
tree | 3fb843e38b658d25591c0b34825c548a99013ef3 /rtl | |
parent | 8836d99ab9af0ee4a9b2077281c1a321c61b1d22 (diff) |
Microcode for ECDH cores.
Diffstat (limited to 'rtl')
-rw-r--r-- | rtl/curve/uop/uop_init_rom_ecdh.v | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/rtl/curve/uop/uop_init_rom_ecdh.v b/rtl/curve/uop/uop_init_rom_ecdh.v new file mode 100644 index 0000000..dc92f2a --- /dev/null +++ b/rtl/curve/uop/uop_init_rom_ecdh.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps + +module uop_init_rom_ecdh + ( + input wire clk, + input wire [ 5: 0] addr, + output reg [19: 0] data + ); + + + // + // Microcode + // +`include "../uop_ecdsa.v" + + + // + // Initialization Microprogram for ECDH Mode + // + always @(posedge clk) + + case (addr) + + 6'd00: data <= {OPCODE_MOV, UOP_SRC_G_X, UOP_SRC_DUMMY, UOP_DST_RX, UOP_EXEC_ALWAYS}; + 6'd01: data <= {OPCODE_MOV, UOP_SRC_G_Y, UOP_SRC_DUMMY, UOP_DST_RY, UOP_EXEC_ALWAYS}; + 6'd02: data <= {OPCODE_MOV, UOP_SRC_ONE, UOP_SRC_DUMMY, UOP_DST_RZ, UOP_EXEC_ALWAYS}; + + default: data <= {OPCODE_RDY, UOP_SRC_DUMMY, UOP_SRC_DUMMY, UOP_DST_DUMMY, UOP_EXEC_ALWAYS}; + + endcase + + +endmodule |