core/hash/sha512 - Verilog implementation of the SHA-512 hash function

Age	Commit message (Collapse)	Author
2018-04-23	Correcting name for t1 and t2 update vectors. Cleaned up constants.	Joachim Strömbergson

2018-04-06	Updated state display. Added cycle count display.	Joachim Strömbergson

2018-04-06	Added registers for t1 and t2. Updated tb to look at update vectors.	Joachim Strömbergson

2018-04-06	Minor cleanup of mask definition to make it easier to understand.	Joachim Strömbergson

2018-04-03	Changed constant declaraiton to use hex radix. Removed now redundant flag ↵	Joachim Strömbergson
	signal assignment.
2018-04-03	Connected all dangling dut ports in the core testbench. Fixed RTL code that ↵	Joachim Strömbergson
	caused event loop in Icarus. Does not change functionality.
2018-04-03	Non functional cleanups: (1) Changed name of round counter to show what is ↵	Joachim Strömbergson
	used for. (2) Fixed timescale and empty parentheses of tasks in testbenches. (3) Fixed targets in Makefile to build if needed.
2015-12-13	whack copyrights	Paul Selkirk

2014-11-06	Fixes of nits in #8 found with the verilator linter.	Joachim Strömbergson

2014-04-05	Adding core and top level testbenches for sha512.	Joachim Strömbergson