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AgeCommit message (Expand)Author
2018-04-25Added pipeline cycle for t1 and t2 calculations. Updated and cleaned up the W...Joachim Strömbergson
2018-04-24Removed redundant code by fusing expression.Joachim Strömbergson
2018-04-24Fixing reg update signals. Fixing names.Joachim Strömbergson
2018-04-23Minor cleanup.Joachim Strömbergson
2018-04-06Added registers for t1 and t2. Updated tb to look at update vectors.Joachim Strömbergson
2018-04-03Changed constant declaraiton to use hex radix. Removed now redundant flag sig...Joachim Strömbergson
2018-04-03Connected all dangling dut ports in the core testbench. Fixed RTL code that c...Joachim Strömbergson
2018-04-03Non functional cleanups: (1) Changed name of round counter to show what is us...Joachim Strömbergson
2018-04-03Added second round state to allow for one cycle propagation of t1 in a future...Joachim Strömbergson
2015-12-13whack copyrightsPaul Selkirk
2015-07-18Adding logic to write state restore data to the state registers.Joachim Strömbergson
2015-07-18Added API logic to set write signals for the state.Joachim Strömbergson
2015-07-18Adding ports in the core to do state restore. Added wires in the top to conne...Joachim Strömbergson
2015-03-31Revert streamlined wrapper, and don't delay register reads.Paul Selkirk
2015-03-17Rearrange cores.Paul Selkirk
2014-11-20Adding work factor processing functionality.Joachim Strömbergson
2014-11-06Fixes of nits in #8 found with the verilator linter.Joachim Strömbergson
2014-09-11Changed to asynch reset.Joachim Strömbergson
2014-04-05Adding source RTL files for the sha512 core.Joachim Strömbergson