| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-12-04 | Added reg on output from w_mem to split long path. Adjusted when w_next is ↵clock_speed | Joachim Strömbergson | |
| set to update w_mem to account for delay cycle. | |||
| 2018-04-25 | Added pipeline cycle for t1 and t2 calculations. Updated and cleaned up the ↵ | Joachim Strömbergson | |
| W message block scheduler to work with pipeline stage. And be less complex. | |||
| 2015-12-13 | whack copyrights | Paul Selkirk | |
| 2014-11-06 | Fixes of nits in #8 found with the verilator linter. | Joachim Strömbergson | |
| 2014-09-11 | Changed to asynch reset. | Joachim Strömbergson | |
| 2014-04-05 | Adding source RTL files for the sha512 core. | Joachim Strömbergson | |
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index : core/hash/sha512 | |
| Verilog implementation of the SHA-512 hash function | git repositories |
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