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core/hash/sha512
clock_speed
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Verilog implementation of the SHA-512 hash function
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2018-12-04
Merged clock speed optimization work.
HEAD
master
Joachim Strömbergson
2018-12-04
Added reg on output from w_mem to split long path. Adjusted when w_next is se...
clock_speed
Joachim Strömbergson
2018-12-04
Compacted the code.
Joachim Strömbergson
2018-10-19
Locked down API write and API digest read access to only be allowed when the ...
Joachim Strömbergson
2018-10-19
Cleaned up the code as part of fixing issues found during the audit.
Joachim Strömbergson
2018-10-16
Added width definitons.
Joachim Strömbergson
2018-04-25
Added pipeline cycle for t1 and t2 calculations. Updated and cleaned up the W...
Joachim Strömbergson
2018-04-24
Removed redundant code by fusing expression.
Joachim Strömbergson
2018-04-24
Fixing reg update signals. Fixing names.
Joachim Strömbergson
2018-04-23
Correcting name for t1 and t2 update vectors. Cleaned up constants.
Joachim Strömbergson
2018-04-23
Minor cleanup.
Joachim Strömbergson
2018-04-06
Updated state display. Added cycle count display.
Joachim Strömbergson
2018-04-06
Added registers for t1 and t2. Updated tb to look at update vectors.
Joachim Strömbergson
2018-04-06
Minor cleanup of mask definition to make it easier to understand.
Joachim Strömbergson
2018-04-06
Added support for dumping T2 inputs and calculations.
Joachim Strömbergson
2018-04-06
Improved digest check and dump to be more usable.
Joachim Strömbergson
2018-04-06
Minor cleanup of names to make the code clearer.
Joachim Strömbergson
2018-04-06
Finally implemented SHA-512-224 digest properly. Added test case for SHA-512-...
Joachim Strömbergson
2018-04-06
Added testcases for other SHA-512 versions per FIPS 180-4.
Joachim Strömbergson
2018-04-05
Removed weird semicolons.
Joachim Strömbergson
2018-04-05
Adding first double block test for SHA-512. Test ok.
Joachim Strömbergson
2018-04-05
Adding message blocks for multi block tests.
Joachim Strömbergson
2018-04-05
Moved tests to separate function to allow for adding multi block message tests.
Joachim Strömbergson
2018-04-05
(1) Added dumping of T1 inputs, calculated values and result needed to pipeli...
Joachim Strömbergson
2018-04-03
Changed constant declaraiton to use hex radix. Removed now redundant flag sig...
Joachim Strömbergson
2018-04-03
Connected all dangling dut ports in the core testbench. Fixed RTL code that c...
Joachim Strömbergson
2018-04-03
Non functional cleanups: (1) Changed name of round counter to show what is us...
Joachim Strömbergson
2018-04-03
Added second round state to allow for one cycle propagation of t1 in a future...
Joachim Strömbergson
2018-03-27
Cleaned up Makefile. Adding lint support.
Joachim Strömbergson
2015-12-13
whack copyrights
Paul Selkirk
2015-07-18
Completed test case for state restore. The state restore functionality works....
Joachim Strömbergson
2015-07-18
Adding initial version of test case for state restore functionality.
Joachim Strömbergson
2015-07-18
Adding logic to write state restore data to the state registers.
Joachim Strömbergson
2015-07-18
Added API logic to set write signals for the state.
Joachim Strömbergson
2015-07-18
Adding ports in the core to do state restore. Added wires in the top to conne...
Joachim Strömbergson
2015-03-31
Revert streamlined wrapper, and don't delay register reads.
Paul Selkirk
2015-03-17
Rearrange cores.
Paul Selkirk
2014-11-20
Adding work factor processing functionality.
Joachim Strömbergson
2014-11-06
Fixes of nits in #8 found with the verilator linter.
Joachim Strömbergson
2014-09-11
Changed to asynch reset.
Joachim Strömbergson
2014-04-05
Adding the Python functional model of the SHA-512 core.
Joachim Strömbergson
2014-04-05
Adding source RTL files for the sha512 core.
Joachim Strömbergson
2014-04-05
Adding core and top level testbenches for sha512.
Joachim Strömbergson
2014-04-05
Adding Makefile for building sha512 simulation targets.
Joachim Strömbergson
2014-04-05
Adding license and README file for the sha512 core.
Joachim Strömbergson