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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-16 10:40:13 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-16 10:40:13 +0200
commit39aff1f475b27926fd5a479b3598977eafb6ee69 (patch)
tree275e2d7afaf2dbec56a1100fc35f20780bcec1d8
parent4a5429f8005ee820a8fa37f6ad09262a3201a129 (diff)
Added width definitons.
-rw-r--r--src/rtl/sha512.v76
-rw-r--r--src/rtl/sha512_w_mem.v2
2 files changed, 39 insertions, 39 deletions
diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v
index 6aa1557..a0e5f9f 100644
--- a/src/rtl/sha512.v
+++ b/src/rtl/sha512.v
@@ -342,46 +342,46 @@ module sha512(
begin
if (!reset_n)
begin
- init_reg <= 0;
- next_reg <= 0;
+ init_reg <= 1'h0;
+ next_reg <= 1'h0;
mode_reg <= MODE_SHA_512;
- work_factor_reg <= 0;
+ work_factor_reg <= 1'h0;
work_factor_num_reg <= DEFAULT_WORK_FACTOR_NUM;
- ready_reg <= 0;
- digest_reg <= {16{32'h00000000}};
- digest_valid_reg <= 0;
- block0_reg <= 32'h00000000;
- block1_reg <= 32'h00000000;
- block2_reg <= 32'h00000000;
- block3_reg <= 32'h00000000;
- block4_reg <= 32'h00000000;
- block5_reg <= 32'h00000000;
- block6_reg <= 32'h00000000;
- block7_reg <= 32'h00000000;
- block8_reg <= 32'h00000000;
- block9_reg <= 32'h00000000;
- block10_reg <= 32'h00000000;
- block11_reg <= 32'h00000000;
- block12_reg <= 32'h00000000;
- block13_reg <= 32'h00000000;
- block14_reg <= 32'h00000000;
- block15_reg <= 32'h00000000;
- block16_reg <= 32'h00000000;
- block17_reg <= 32'h00000000;
- block18_reg <= 32'h00000000;
- block19_reg <= 32'h00000000;
- block20_reg <= 32'h00000000;
- block21_reg <= 32'h00000000;
- block22_reg <= 32'h00000000;
- block23_reg <= 32'h00000000;
- block24_reg <= 32'h00000000;
- block25_reg <= 32'h00000000;
- block26_reg <= 32'h00000000;
- block27_reg <= 32'h00000000;
- block28_reg <= 32'h00000000;
- block29_reg <= 32'h00000000;
- block30_reg <= 32'h00000000;
- block31_reg <= 32'h00000000;
+ ready_reg <= 1'h0;
+ digest_reg <= 512'h0;
+ digest_valid_reg <= 1'h0;
+ block0_reg <= 32'h0;
+ block1_reg <= 32'h0;
+ block2_reg <= 32'h0;
+ block3_reg <= 32'h0;
+ block4_reg <= 32'h0;
+ block5_reg <= 32'h0;
+ block6_reg <= 32'h0;
+ block7_reg <= 32'h0;
+ block8_reg <= 32'h0;
+ block9_reg <= 32'h0;
+ block10_reg <= 32'h0;
+ block11_reg <= 32'h0;
+ block12_reg <= 32'h0;
+ block13_reg <= 32'h0;
+ block14_reg <= 32'h0;
+ block15_reg <= 32'h0;
+ block16_reg <= 32'h0;
+ block17_reg <= 32'h0;
+ block18_reg <= 32'h0;
+ block19_reg <= 32'h0;
+ block20_reg <= 32'h0;
+ block21_reg <= 32'h0;
+ block22_reg <= 32'h0;
+ block23_reg <= 32'h0;
+ block24_reg <= 32'h0;
+ block25_reg <= 32'h0;
+ block26_reg <= 32'h0;
+ block27_reg <= 32'h0;
+ block28_reg <= 32'h0;
+ block29_reg <= 32'h0;
+ block30_reg <= 32'h0;
+ block31_reg <= 32'h0;
end
else
begin
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index e0a6775..f4f8a1c 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -123,7 +123,7 @@ module sha512_w_mem(
w_mem[13] <= 64'h0;
w_mem[14] <= 64'h0;
w_mem[15] <= 64'h0;
- w_ctr_reg <= 7'h00;
+ w_ctr_reg <= 7'h0;
end
else
begin