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-rw-r--r--src/rtl/sha512.v931
1 files changed, 78 insertions, 853 deletions
diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v
index a0e5f9f..085783b 100644
--- a/src/rtl/sha512.v
+++ b/src/rtl/sha512.v
@@ -75,36 +75,6 @@ module sha512(
parameter ADDR_WORK_FACTOR_NUM = 8'h0a;
parameter ADDR_BLOCK0 = 8'h10;
- parameter ADDR_BLOCK1 = 8'h11;
- parameter ADDR_BLOCK2 = 8'h12;
- parameter ADDR_BLOCK3 = 8'h13;
- parameter ADDR_BLOCK4 = 8'h14;
- parameter ADDR_BLOCK5 = 8'h15;
- parameter ADDR_BLOCK6 = 8'h16;
- parameter ADDR_BLOCK7 = 8'h17;
- parameter ADDR_BLOCK8 = 8'h18;
- parameter ADDR_BLOCK9 = 8'h19;
- parameter ADDR_BLOCK10 = 8'h1a;
- parameter ADDR_BLOCK11 = 8'h1b;
- parameter ADDR_BLOCK12 = 8'h1c;
- parameter ADDR_BLOCK13 = 8'h1d;
- parameter ADDR_BLOCK14 = 8'h1e;
- parameter ADDR_BLOCK15 = 8'h1f;
- parameter ADDR_BLOCK16 = 8'h20;
- parameter ADDR_BLOCK17 = 8'h21;
- parameter ADDR_BLOCK18 = 8'h22;
- parameter ADDR_BLOCK19 = 8'h23;
- parameter ADDR_BLOCK20 = 8'h24;
- parameter ADDR_BLOCK21 = 8'h25;
- parameter ADDR_BLOCK22 = 8'h26;
- parameter ADDR_BLOCK23 = 8'h27;
- parameter ADDR_BLOCK24 = 8'h28;
- parameter ADDR_BLOCK25 = 8'h29;
- parameter ADDR_BLOCK26 = 8'h2a;
- parameter ADDR_BLOCK27 = 8'h2b;
- parameter ADDR_BLOCK28 = 8'h2c;
- parameter ADDR_BLOCK29 = 8'h2d;
- parameter ADDR_BLOCK30 = 8'h2e;
parameter ADDR_BLOCK31 = 8'h2f;
parameter ADDR_DIGEST0 = 8'h40;
@@ -126,7 +96,7 @@ module sha512(
parameter CORE_NAME0 = 32'h73686132; // "sha2"
parameter CORE_NAME1 = 32'h2d353132; // "-512"
- parameter CORE_VERSION = 32'h302e3830; // "0.80"
+ parameter CORE_VERSION = 32'h302e3831; // "0.81"
parameter MODE_SHA_512_224 = 2'h0;
parameter MODE_SHA_512_256 = 2'h1;
@@ -162,70 +132,8 @@ module sha512(
reg ready_reg;
- reg [31 : 0] block0_reg;
- reg block0_we;
- reg [31 : 0] block1_reg;
- reg block1_we;
- reg [31 : 0] block2_reg;
- reg block2_we;
- reg [31 : 0] block3_reg;
- reg block3_we;
- reg [31 : 0] block4_reg;
- reg block4_we;
- reg [31 : 0] block5_reg;
- reg block5_we;
- reg [31 : 0] block6_reg;
- reg block6_we;
- reg [31 : 0] block7_reg;
- reg block7_we;
- reg [31 : 0] block8_reg;
- reg block8_we;
- reg [31 : 0] block9_reg;
- reg block9_we;
- reg [31 : 0] block10_reg;
- reg block10_we;
- reg [31 : 0] block11_reg;
- reg block11_we;
- reg [31 : 0] block12_reg;
- reg block12_we;
- reg [31 : 0] block13_reg;
- reg block13_we;
- reg [31 : 0] block14_reg;
- reg block14_we;
- reg [31 : 0] block15_reg;
- reg block15_we;
- reg [31 : 0] block16_reg;
- reg block16_we;
- reg [31 : 0] block17_reg;
- reg block17_we;
- reg [31 : 0] block18_reg;
- reg block18_we;
- reg [31 : 0] block19_reg;
- reg block19_we;
- reg [31 : 0] block20_reg;
- reg block20_we;
- reg [31 : 0] block21_reg;
- reg block21_we;
- reg [31 : 0] block22_reg;
- reg block22_we;
- reg [31 : 0] block23_reg;
- reg block23_we;
- reg [31 : 0] block24_reg;
- reg block24_we;
- reg [31 : 0] block25_reg;
- reg block25_we;
- reg [31 : 0] block26_reg;
- reg block26_we;
- reg [31 : 0] block27_reg;
- reg block27_we;
- reg [31 : 0] block28_reg;
- reg block28_we;
- reg [31 : 0] block29_reg;
- reg block29_we;
- reg [31 : 0] block30_reg;
- reg block30_we;
- reg [31 : 0] block31_reg;
- reg block31_we;
+ reg [31 : 0] block_reg [0 : 31];
+ reg block_we;
reg [511 : 0] digest_reg;
reg digest_valid_reg;
@@ -234,16 +142,13 @@ module sha512(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- wire core_init;
- wire core_next;
- wire [1 : 0] core_mode;
- wire core_work_factor;
- wire [31 : 0] core_work_factor_num;
wire core_ready;
wire [1023 : 0] core_block;
wire [511 : 0] core_digest;
wire core_digest_valid;
+ reg [4 : 0] block_addr;
+
reg state00_we;
reg state01_we;
reg state02_we;
@@ -261,7 +166,6 @@ module sha512(
reg state14_we;
reg state15_we;
-
reg [31 : 0] tmp_read_data;
reg tmp_error;
@@ -269,22 +173,14 @@ module sha512(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
- assign core_init = init_reg;
-
- assign core_next = next_reg;
-
- assign core_mode = mode_reg;
-
- assign core_work_factor = work_factor_reg;
- assign core_work_factor_num = work_factor_num_reg;
-
- assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg, block4_reg,
- block5_reg, block6_reg, block7_reg, block8_reg, block9_reg,
- block10_reg, block11_reg, block12_reg, block13_reg, block14_reg,
- block15_reg, block16_reg, block17_reg, block18_reg, block19_reg,
- block20_reg, block21_reg, block22_reg, block23_reg, block24_reg,
- block25_reg, block26_reg, block27_reg, block28_reg, block29_reg,
- block30_reg, block31_reg};
+ assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
+ block_reg[04], block_reg[05], block_reg[06], block_reg[07],
+ block_reg[08], block_reg[09], block_reg[10], block_reg[11],
+ block_reg[12], block_reg[13], block_reg[14], block_reg[15],
+ block_reg[16], block_reg[17], block_reg[18], block_reg[19],
+ block_reg[20], block_reg[21], block_reg[22], block_reg[23],
+ block_reg[24], block_reg[25], block_reg[26], block_reg[27],
+ block_reg[28], block_reg[29], block_reg[30], block_reg[31]};
assign read_data = tmp_read_data;
assign error = tmp_error;
@@ -297,12 +193,12 @@ module sha512(
.clk(clk),
.reset_n(reset_n),
- .init(core_init),
- .next(core_next),
- .mode(core_mode),
+ .init(init_reg),
+ .next(next_reg),
+ .mode(mode_reg),
- .work_factor(core_work_factor),
- .work_factor_num(core_work_factor_num),
+ .work_factor(work_factor_reg),
+ .work_factor_num(work_factor_num_reg),
.block(core_block),
@@ -339,9 +235,14 @@ module sha512(
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
- begin
+ begin : reg_update
+ integer i;
+
if (!reset_n)
begin
+ for (i = 0 ; i < 32 ; i = i + 1)
+ block_reg[i] <= 32'h0;
+
init_reg <= 1'h0;
next_reg <= 1'h0;
mode_reg <= MODE_SHA_512;
@@ -350,274 +251,33 @@ module sha512(
ready_reg <= 1'h0;
digest_reg <= 512'h0;
digest_valid_reg <= 1'h0;
- block0_reg <= 32'h0;
- block1_reg <= 32'h0;
- block2_reg <= 32'h0;
- block3_reg <= 32'h0;
- block4_reg <= 32'h0;
- block5_reg <= 32'h0;
- block6_reg <= 32'h0;
- block7_reg <= 32'h0;
- block8_reg <= 32'h0;
- block9_reg <= 32'h0;
- block10_reg <= 32'h0;
- block11_reg <= 32'h0;
- block12_reg <= 32'h0;
- block13_reg <= 32'h0;
- block14_reg <= 32'h0;
- block15_reg <= 32'h0;
- block16_reg <= 32'h0;
- block17_reg <= 32'h0;
- block18_reg <= 32'h0;
- block19_reg <= 32'h0;
- block20_reg <= 32'h0;
- block21_reg <= 32'h0;
- block22_reg <= 32'h0;
- block23_reg <= 32'h0;
- block24_reg <= 32'h0;
- block25_reg <= 32'h0;
- block26_reg <= 32'h0;
- block27_reg <= 32'h0;
- block28_reg <= 32'h0;
- block29_reg <= 32'h0;
- block30_reg <= 32'h0;
- block31_reg <= 32'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
-
- if (init_we)
- begin
- init_reg <= init_new;
- end
-
- if (next_we)
- begin
- next_reg <= next_new;
- end
+ init_reg <= init_new;
+ next_reg <= next_new;
if (mode_we)
- begin
- mode_reg <= mode_new;
- end
+ mode_reg <= mode_new;
if (work_factor_we)
- begin
- work_factor_reg <= work_factor_new;
- end
+ work_factor_reg <= work_factor_new;
if (work_factor_num_we)
- begin
- work_factor_num_reg <= write_data;
- end
+ work_factor_num_reg <= write_data;
if (core_digest_valid)
- begin
- digest_reg <= core_digest;
- end
-
- if (block0_we)
- begin
- block0_reg <= write_data;
- end
-
- if (block1_we)
- begin
- block1_reg <= write_data;
- end
-
- if (block2_we)
- begin
- block2_reg <= write_data;
- end
-
- if (block3_we)
- begin
- block3_reg <= write_data;
- end
-
- if (block4_we)
- begin
- block4_reg <= write_data;
- end
-
- if (block5_we)
- begin
- block5_reg <= write_data;
- end
-
- if (block6_we)
- begin
- block6_reg <= write_data;
- end
-
- if (block7_we)
- begin
- block7_reg <= write_data;
- end
-
- if (block8_we)
- begin
- block8_reg <= write_data;
- end
-
- if (block9_we)
- begin
- block9_reg <= write_data;
- end
-
- if (block10_we)
- begin
- block10_reg <= write_data;
- end
-
- if (block11_we)
- begin
- block11_reg <= write_data;
- end
-
- if (block12_we)
- begin
- block12_reg <= write_data;
- end
-
- if (block13_we)
- begin
- block13_reg <= write_data;
- end
-
- if (block14_we)
- begin
- block14_reg <= write_data;
- end
-
- if (block15_we)
- begin
- block15_reg <= write_data;
- end
-
- if (block16_we)
- begin
- block16_reg <= write_data;
- end
-
- if (block17_we)
- begin
- block17_reg <= write_data;
- end
-
- if (block18_we)
- begin
- block18_reg <= write_data;
- end
-
- if (block19_we)
- begin
- block19_reg <= write_data;
- end
-
- if (block20_we)
- begin
- block20_reg <= write_data;
- end
-
- if (block21_we)
- begin
- block21_reg <= write_data;
- end
-
- if (block22_we)
- begin
- block22_reg <= write_data;
- end
-
- if (block23_we)
- begin
- block23_reg <= write_data;
- end
-
- if (block24_we)
- begin
- block24_reg <= write_data;
- end
-
- if (block25_we)
- begin
- block25_reg <= write_data;
- end
-
- if (block26_we)
- begin
- block26_reg <= write_data;
- end
-
- if (block27_we)
- begin
- block27_reg <= write_data;
- end
-
- if (block28_we)
- begin
- block28_reg <= write_data;
- end
-
- if (block29_we)
- begin
- block29_reg <= write_data;
- end
-
- if (block30_we)
- begin
- block30_reg <= write_data;
- end
+ digest_reg <= core_digest;
- if (block31_we)
- begin
- block31_reg <= write_data;
- end
+ if (block_we)
+ block_reg[block_addr] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
- // flag_reset
- //
- // Logic to reset init and next flags that has been set.
- //----------------------------------------------------------------
- always @*
- begin : flag_reset
- init_new = 0;
- init_we = 0;
- next_new = 0;
- next_we = 0;
-
- if (init_set)
- begin
- init_new = 1;
- init_we = 1;
- end
- else if (init_reg)
- begin
- init_new = 0;
- init_we = 1;
- end
-
- if (next_set)
- begin
- next_new = 1;
- next_we = 1;
- end
- else if (next_reg)
- begin
- next_new = 0;
- next_we = 1;
- end
- end
-
-
- //----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
@@ -625,78 +285,51 @@ module sha512(
//----------------------------------------------------------------
always @*
begin : api_logic
- init_set = 0;
- next_set = 0;
- mode_new = 2'b00;
- mode_we = 0;
- work_factor_new = 0;
- work_factor_we = 0;
- work_factor_num_we = 0;
- block0_we = 0;
- block1_we = 0;
- block2_we = 0;
- block3_we = 0;
- block4_we = 0;
- block5_we = 0;
- block6_we = 0;
- block7_we = 0;
- block8_we = 0;
- block9_we = 0;
- block10_we = 0;
- block11_we = 0;
- block12_we = 0;
- block13_we = 0;
- block14_we = 0;
- block15_we = 0;
- block16_we = 0;
- block17_we = 0;
- block18_we = 0;
- block19_we = 0;
- block20_we = 0;
- block21_we = 0;
- block22_we = 0;
- block23_we = 0;
- block24_we = 0;
- block25_we = 0;
- block26_we = 0;
- block27_we = 0;
- block28_we = 0;
- block29_we = 0;
- block30_we = 0;
- block31_we = 0;
- state00_we = 0;
- state01_we = 0;
- state02_we = 0;
- state03_we = 0;
- state04_we = 0;
- state05_we = 0;
- state06_we = 0;
- state07_we = 0;
- state08_we = 0;
- state09_we = 0;
- state10_we = 0;
- state11_we = 0;
- state12_we = 0;
- state13_we = 0;
- state14_we = 0;
- state15_we = 0;
+ init_new = 1'h0;
+ next_new = 1'h0;
+ mode_new = MODE_SHA_512;
+ mode_we = 1'h0;
+ work_factor_new = 1'h0;
+ work_factor_we = 1'h0;
+ work_factor_num_we = 1'h0;
+ block_we = 1'h0;
+ state00_we = 1'h0;
+ state01_we = 1'h0;
+ state02_we = 1'h0;
+ state03_we = 1'h0;
+ state04_we = 1'h0;
+ state05_we = 1'h0;
+ state06_we = 1'h0;
+ state07_we = 1'h0;
+ state08_we = 1'h0;
+ state09_we = 1'h0;
+ state10_we = 1'h0;
+ state11_we = 1'h0;
+ state12_we = 1'h0;
+ state13_we = 1'h0;
+ state14_we = 1'h0;
+ state15_we = 1'h0;
tmp_read_data = 32'h00000000;
- tmp_error = 0;
+ tmp_error = 1'h0;
+
+ block_addr = address[4 : 0] - ADDR_BLOCK0[4 : 0];
if (cs)
begin
if (we)
begin
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK31))
+ block_we = 1'h1;
+
case (address)
- // Write operations.
ADDR_CTRL:
begin
- init_set = write_data[CTRL_INIT_BIT];
- next_set = write_data[CTRL_NEXT_BIT];
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
mode_new = write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
+ mode_we = 1'h1;
work_factor_new = write_data[CTRL_WORK_FACTOR_BIT];
- work_factor_we = 1;
- mode_we = 1;
+ work_factor_we = 1'h1;
end
ADDR_WORK_FACTOR_NUM:
@@ -704,166 +337,6 @@ module sha512(
work_factor_num_we = 1;
end
- ADDR_BLOCK0:
- begin
- block0_we = 1;
- end
-
- ADDR_BLOCK1:
- begin
- block1_we = 1;
- end
-
- ADDR_BLOCK2:
- begin
- block2_we = 1;
- end
-
- ADDR_BLOCK3:
- begin
- block3_we = 1;
- end
-
- ADDR_BLOCK4:
- begin
- block4_we = 1;
- end
-
- ADDR_BLOCK5:
- begin
- block5_we = 1;
- end
-
- ADDR_BLOCK6:
- begin
- block6_we = 1;
- end
-
- ADDR_BLOCK7:
- begin
- block7_we = 1;
- end
-
- ADDR_BLOCK8:
- begin
- block8_we = 1;
- end
-
- ADDR_BLOCK9:
- begin
- block9_we = 1;
- end
-
- ADDR_BLOCK10:
- begin
- block10_we = 1;
- end
-
- ADDR_BLOCK11:
- begin
- block11_we = 1;
- end
-
- ADDR_BLOCK12:
- begin
- block12_we = 1;
- end
-
- ADDR_BLOCK13:
- begin
- block13_we = 1;
- end
-
- ADDR_BLOCK14:
- begin
- block14_we = 1;
- end
-
- ADDR_BLOCK15:
- begin
- block15_we = 1;
- end
-
- ADDR_BLOCK16:
- begin
- block16_we = 1;
- end
-
- ADDR_BLOCK17:
- begin
- block17_we = 1;
- end
-
- ADDR_BLOCK18:
- begin
- block18_we = 1;
- end
-
- ADDR_BLOCK19:
- begin
- block19_we = 1;
- end
-
- ADDR_BLOCK20:
- begin
- block20_we = 1;
- end
-
- ADDR_BLOCK21:
- begin
- block21_we = 1;
- end
-
- ADDR_BLOCK22:
- begin
- block22_we = 1;
- end
-
- ADDR_BLOCK23:
- begin
- block23_we = 1;
- end
-
- ADDR_BLOCK24:
- begin
- block24_we = 1;
- end
-
- ADDR_BLOCK25:
- begin
- block25_we = 1;
- end
-
- ADDR_BLOCK26:
- begin
- block26_we = 1;
- end
-
- ADDR_BLOCK27:
- begin
- block27_we = 1;
- end
-
- ADDR_BLOCK28:
- begin
- block28_we = 1;
- end
-
- ADDR_BLOCK29:
- begin
- block29_we = 1;
- end
-
- ADDR_BLOCK30:
- begin
- block30_we = 1;
- end
-
- ADDR_BLOCK31:
- begin
- block31_we = 1;
- end
-
ADDR_DIGEST0:
state00_we = 1;
@@ -921,278 +394,30 @@ module sha512(
else
begin
+ if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST15))
+ tmp_read_data = digest_reg[(15 - (address - ADDR_DIGEST0)) * 32 +: 32];
+
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK31))
+ tmp_read_data = block_reg[address[4 : 0]];
+
case (address)
- // Read operations.
ADDR_NAME0:
- begin
- tmp_read_data = CORE_NAME0;
- end
+ tmp_read_data = CORE_NAME0;
ADDR_NAME1:
- begin
- tmp_read_data = CORE_NAME1;
- end
+ tmp_read_data = CORE_NAME1;
ADDR_VERSION:
- begin
- tmp_read_data = CORE_VERSION;
- end
+ tmp_read_data = CORE_VERSION;
ADDR_CTRL:
- begin
- tmp_read_data = {24'h000000, work_factor_reg, 3'b000,
- mode_reg, next_reg, init_reg};
- end
+ tmp_read_data = {24'h000000, work_factor_reg, 3'b000, mode_reg, next_reg, init_reg};
ADDR_STATUS:
- begin
- tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
- end
+ tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
ADDR_WORK_FACTOR_NUM:
- begin
- tmp_read_data = work_factor_num_reg;
- end
-
- ADDR_BLOCK0:
- begin
- tmp_read_data = block0_reg;
- end
-
- ADDR_BLOCK1:
- begin
- tmp_read_data = block1_reg;
- end
-
- ADDR_BLOCK2:
- begin
- tmp_read_data = block2_reg;
- end
-
- ADDR_BLOCK3:
- begin
- tmp_read_data = block3_reg;
- end
-
- ADDR_BLOCK4:
- begin
- tmp_read_data = block4_reg;
- end
-
- ADDR_BLOCK5:
- begin
- tmp_read_data = block5_reg;
- end
-
- ADDR_BLOCK6:
- begin
- tmp_read_data = block6_reg;
- end
-
- ADDR_BLOCK7:
- begin
- tmp_read_data = block7_reg;
- end
-
- ADDR_BLOCK8:
- begin
- tmp_read_data = block8_reg;
- end
-
- ADDR_BLOCK9:
- begin
- tmp_read_data = block9_reg;
- end
-
- ADDR_BLOCK10:
- begin
- tmp_read_data = block10_reg;
- end
-
- ADDR_BLOCK11:
- begin
- tmp_read_data = block11_reg;
- end
-
- ADDR_BLOCK12:
- begin
- tmp_read_data = block12_reg;
- end
-
- ADDR_BLOCK13:
- begin
- tmp_read_data = block13_reg;
- end
-
- ADDR_BLOCK14:
- begin
- tmp_read_data = block14_reg;
- end
-
- ADDR_BLOCK15:
- begin
- tmp_read_data = block15_reg;
- end
-
- ADDR_BLOCK16:
- begin
- tmp_read_data = block16_reg;
- end
-
- ADDR_BLOCK17:
- begin
- tmp_read_data = block17_reg;
- end
-
- ADDR_BLOCK18:
- begin
- tmp_read_data = block18_reg;
- end
-
- ADDR_BLOCK19:
- begin
- tmp_read_data = block19_reg;
- end
-
- ADDR_BLOCK20:
- begin
- tmp_read_data = block20_reg;
- end
-
- ADDR_BLOCK21:
- begin
- tmp_read_data = block21_reg;
- end
-
- ADDR_BLOCK22:
- begin
- tmp_read_data = block22_reg;
- end
-
- ADDR_BLOCK23:
- begin
- tmp_read_data = block23_reg;
- end
-
- ADDR_BLOCK24:
- begin
- tmp_read_data = block24_reg;
- end
-
- ADDR_BLOCK25:
- begin
- tmp_read_data = block25_reg;
- end
-
- ADDR_BLOCK26:
- begin
- tmp_read_data = block26_reg;
- end
-
- ADDR_BLOCK27:
- begin
- tmp_read_data = block27_reg;
- end
-
- ADDR_BLOCK28:
- begin
- tmp_read_data = block28_reg;
- end
-
- ADDR_BLOCK29:
- begin
- tmp_read_data = block29_reg;
- end
-
- ADDR_BLOCK30:
- begin
- tmp_read_data = block30_reg;
- end
-
- ADDR_BLOCK31:
- begin
- tmp_read_data = block31_reg;
- end
-
- ADDR_DIGEST0:
- begin
- tmp_read_data = digest_reg[511 : 480];
- end
-
- ADDR_DIGEST1:
- begin
- tmp_read_data = digest_reg[479 : 448];
- end
-
- ADDR_DIGEST2:
- begin
- tmp_read_data = digest_reg[447 : 416];
- end
-
- ADDR_DIGEST3:
- begin
- tmp_read_data = digest_reg[415 : 384];
- end
-
- ADDR_DIGEST4:
- begin
- tmp_read_data = digest_reg[383 : 352];
- end
-
- ADDR_DIGEST5:
- begin
- tmp_read_data = digest_reg[351 : 320];
- end
-
- ADDR_DIGEST6:
- begin
- tmp_read_data = digest_reg[319 : 288];
- end
-
- ADDR_DIGEST7:
- begin
- tmp_read_data = digest_reg[287 : 256];
- end
-
- ADDR_DIGEST8:
- begin
- tmp_read_data = digest_reg[255 : 224];
- end
-
- ADDR_DIGEST9:
- begin
- tmp_read_data = digest_reg[223 : 192];
- end
-
- ADDR_DIGEST10:
- begin
- tmp_read_data = digest_reg[191 : 160];
- end
-
- ADDR_DIGEST11:
- begin
- tmp_read_data = digest_reg[159 : 128];
- end
-
- ADDR_DIGEST12:
- begin
- tmp_read_data = digest_reg[127 : 96];
- end
-
- ADDR_DIGEST13:
- begin
- tmp_read_data = digest_reg[95 : 64];
- end
-
- ADDR_DIGEST14:
- begin
- tmp_read_data = digest_reg[63 : 32];
- end
-
- ADDR_DIGEST15:
- begin
- tmp_read_data = digest_reg[31 : 0];
- end
+ tmp_read_data = work_factor_num_reg;
default:
begin
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 02:07:30 +0000