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-rw-r--r--src/rtl/sha512_core.v10
-rw-r--r--src/rtl/sha512_w_mem.v153
2 files changed, 59 insertions, 104 deletions
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index e855f76..407f84c 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -498,11 +498,11 @@ module sha512_core(
if (state_update)
begin
- a_new = t1_new + t2_new;
+ a_new = t1_reg + t2_reg;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
- e_new = d_reg + t1_new;
+ e_new = d_reg + t1_reg;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
@@ -652,8 +652,14 @@ module sha512_core(
sha512_ctrl_new = CTRL_DONE;
sha512_ctrl_we = 1;
end
+ else
+ begin
+ sha512_ctrl_new = CTRL_T1_T2;
+ sha512_ctrl_we = 1;
+ end
end
+
CTRL_DONE:
begin
if ((work_factor) && (!work_factor_ctr_done))
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index 15fd564..e0a6775 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -82,12 +82,6 @@ module sha512_w_mem(
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
- reg w_ctr_inc;
- reg w_ctr_rst;
-
- reg sha512_w_mem_ctrl_reg;
- reg sha512_w_mem_ctrl_new;
- reg sha512_w_mem_ctrl_we;
//----------------------------------------------------------------
@@ -113,24 +107,23 @@ module sha512_w_mem(
begin : reg_update
if (!reset_n)
begin
- w_mem[00] <= 64'h0000000000000000;
- w_mem[01] <= 64'h0000000000000000;
- w_mem[02] <= 64'h0000000000000000;
- w_mem[03] <= 64'h0000000000000000;
- w_mem[04] <= 64'h0000000000000000;
- w_mem[05] <= 64'h0000000000000000;
- w_mem[06] <= 64'h0000000000000000;
- w_mem[07] <= 64'h0000000000000000;
- w_mem[08] <= 64'h0000000000000000;
- w_mem[09] <= 64'h0000000000000000;
- w_mem[10] <= 64'h0000000000000000;
- w_mem[11] <= 64'h0000000000000000;
- w_mem[12] <= 64'h0000000000000000;
- w_mem[13] <= 64'h0000000000000000;
- w_mem[14] <= 64'h0000000000000000;
- w_mem[15] <= 64'h0000000000000000;
+ w_mem[00] <= 64'h0;
+ w_mem[01] <= 64'h0;
+ w_mem[02] <= 64'h0;
+ w_mem[03] <= 64'h0;
+ w_mem[04] <= 64'h0;
+ w_mem[05] <= 64'h0;
+ w_mem[06] <= 64'h0;
+ w_mem[07] <= 64'h0;
+ w_mem[08] <= 64'h0;
+ w_mem[09] <= 64'h0;
+ w_mem[10] <= 64'h0;
+ w_mem[11] <= 64'h0;
+ w_mem[12] <= 64'h0;
+ w_mem[13] <= 64'h0;
+ w_mem[14] <= 64'h0;
+ w_mem[15] <= 64'h0;
w_ctr_reg <= 7'h00;
- sha512_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
@@ -158,11 +151,6 @@ module sha512_w_mem(
begin
w_ctr_reg <= w_ctr_new;
end
-
- if (sha512_w_mem_ctrl_we)
- begin
- sha512_w_mem_ctrl_reg <= sha512_w_mem_ctrl_new;
- end
end
end // reg_update
@@ -201,39 +189,24 @@ module sha512_w_mem(
reg [63 : 0] d0;
reg [63 : 0] d1;
- w_mem00_new = 64'h0000000000000000;
- w_mem01_new = 64'h0000000000000000;
- w_mem02_new = 64'h0000000000000000;
- w_mem03_new = 64'h0000000000000000;
- w_mem04_new = 64'h0000000000000000;
- w_mem05_new = 64'h0000000000000000;
- w_mem06_new = 64'h0000000000000000;
- w_mem07_new = 64'h0000000000000000;
- w_mem08_new = 64'h0000000000000000;
- w_mem09_new = 64'h0000000000000000;
- w_mem10_new = 64'h0000000000000000;
- w_mem11_new = 64'h0000000000000000;
- w_mem12_new = 64'h0000000000000000;
- w_mem13_new = 64'h0000000000000000;
- w_mem14_new = 64'h0000000000000000;
- w_mem15_new = 64'h0000000000000000;
+ w_mem00_new = 64'h0;
+ w_mem01_new = 64'h0;
+ w_mem02_new = 64'h0;
+ w_mem03_new = 64'h0;
+ w_mem04_new = 64'h0;
+ w_mem05_new = 64'h0;
+ w_mem06_new = 64'h0;
+ w_mem07_new = 64'h0;
+ w_mem08_new = 64'h0;
+ w_mem09_new = 64'h0;
+ w_mem10_new = 64'h0;
+ w_mem11_new = 64'h0;
+ w_mem12_new = 64'h0;
+ w_mem13_new = 64'h0;
+ w_mem14_new = 64'h0;
+ w_mem15_new = 64'h0;
w_mem_we = 0;
- w_0 = w_mem[0];
- w_1 = w_mem[1];
- w_9 = w_mem[9];
- w_14 = w_mem[14];
-
- d0 = {w_1[0], w_1[63 : 1]} ^ // ROTR1
- {w_1[7 : 0], w_1[63 : 8]} ^ // ROTR8
- {7'b0000000, w_1[63 : 7]}; // SHR7
-
- d1 = {w_14[18 : 0], w_14[63 : 19]} ^ // ROTR19
- {w_14[60 : 0], w_14[63 : 61]} ^ // ROTR61
- {6'b000000, w_14[63 : 6]}; // SHR6
-
- w_new = w_0 + d0 + w_9 + d1;
-
if (init)
begin
w_mem00_new = block[1023 : 960];
@@ -254,7 +227,23 @@ module sha512_w_mem(
w_mem15_new = block[63 : 0];
w_mem_we = 1;
end
- else if (w_ctr_reg > 15)
+
+ w_0 = w_mem[0];
+ w_1 = w_mem[1];
+ w_9 = w_mem[9];
+ w_14 = w_mem[14];
+
+ d0 = {w_1[0], w_1[63 : 1]} ^ // ROTR1
+ {w_1[7 : 0], w_1[63 : 8]} ^ // ROTR8
+ {7'b0000000, w_1[63 : 7]}; // SHR7
+
+ d1 = {w_14[18 : 0], w_14[63 : 19]} ^ // ROTR19
+ {w_14[60 : 0], w_14[63 : 61]} ^ // ROTR61
+ {6'b000000, w_14[63 : 6]}; // SHR6
+
+ w_new = w_0 + d0 + w_9 + d1;
+
+ if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
@@ -287,59 +276,19 @@ module sha512_w_mem(
w_ctr_new = 0;
w_ctr_we = 0;
- if (w_ctr_rst)
+ if (init)
begin
w_ctr_new = 7'h00;
w_ctr_we = 1;
end
- if (w_ctr_inc)
+ if (next)
begin
w_ctr_new = w_ctr_reg + 7'h01;
w_ctr_we = 1;
end
end // w_ctr
-
- //----------------------------------------------------------------
- // sha512_w_mem_fsm
- // Logic for the w shedule FSM.
- //----------------------------------------------------------------
- always @*
- begin : sha512_w_mem_fsm
- w_ctr_rst = 0;
- w_ctr_inc = 0;
-
- sha512_w_mem_ctrl_new = CTRL_IDLE;
- sha512_w_mem_ctrl_we = 0;
-
- case (sha512_w_mem_ctrl_reg)
- CTRL_IDLE:
- begin
- if (init)
- begin
- w_ctr_rst = 1;
- sha512_w_mem_ctrl_new = CTRL_UPDATE;
- sha512_w_mem_ctrl_we = 1;
- end
- end
-
- CTRL_UPDATE:
- begin
- if (next)
- begin
- w_ctr_inc = 1;
- end
-
- if (w_ctr_reg == 7'h3f)
- begin
- sha512_w_mem_ctrl_new = CTRL_IDLE;
- sha512_w_mem_ctrl_we = 1;
- end
- end
- endcase // case (sha512_ctrl_reg)
- end // sha512_ctrl_fsm
-
endmodule // sha512_w_mem
//======================================================================
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