1 files changed, 2 insertions, 2 deletions
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index 57e6d68..47113b9 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -105,10 +105,10 @@ module sha512_w_mem(
   //----------------------------------------------------------------
   // reg_update
   // Update functionality for all registers in the core.
-  // All registers are positive edge triggered with synchronous
+  // All registers are positive edge triggered with asynchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
       if (!reset_n)
         begin