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-rw-r--r--src/rtl/sha512_w_mem.v32
1 files changed, 13 insertions, 19 deletions
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index f4f8a1c..4aadb50 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -83,12 +83,14 @@ module sha512_w_mem(
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
+ reg [63 : 0] w_reg;
+ reg [63 : 0] w_new;
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] w_tmp;
- reg [63 : 0] w_new;
//----------------------------------------------------------------
@@ -105,28 +107,20 @@ module sha512_w_mem(
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
+ integer i;
+
if (!reset_n)
begin
- w_mem[00] <= 64'h0;
- w_mem[01] <= 64'h0;
- w_mem[02] <= 64'h0;
- w_mem[03] <= 64'h0;
- w_mem[04] <= 64'h0;
- w_mem[05] <= 64'h0;
- w_mem[06] <= 64'h0;
- w_mem[07] <= 64'h0;
- w_mem[08] <= 64'h0;
- w_mem[09] <= 64'h0;
- w_mem[10] <= 64'h0;
- w_mem[11] <= 64'h0;
- w_mem[12] <= 64'h0;
- w_mem[13] <= 64'h0;
- w_mem[14] <= 64'h0;
- w_mem[15] <= 64'h0;
- w_ctr_reg <= 7'h0;
+ for (i = 0 ; i < 16 ; i = i + 1)
+ w_mem[i] <= 64'h0;
+
+ w_ctr_reg <= 7'h0;
+ w_reg <= 64'h0;
end
else
begin
+ w_reg <= w_new;
+
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
@@ -169,7 +163,7 @@ module sha512_w_mem(
end
else
begin
- w_tmp = w_new;
+ w_tmp = w_reg;
end
end // select_w