diff options
Diffstat (limited to 'src/rtl/sha512_core.v')
| -rw-r--r-- | src/rtl/sha512_core.v | 187 |
1 files changed, 130 insertions, 57 deletions
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index 44af0b1..12742a8 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -45,6 +45,9 @@ module sha512_core( input wire next, input wire [1 : 0] mode, + input wire work_factor, + input wire [31 : 0] work_factor_num, + input wire [1023 : 0] block, output wire ready, @@ -108,6 +111,13 @@ module sha512_core( reg t_ctr_inc; reg t_ctr_rst; + reg [31 : 0] work_factor_ctr_reg; + reg [31 : 0] work_factor_ctr_new; + reg work_factor_ctr_rst; + reg work_factor_ctr_inc; + reg work_factor_ctr_done; + reg work_factor_ctr_we; + reg digest_valid_reg; reg digest_valid_new; reg digest_valid_we; @@ -205,25 +215,26 @@ module sha512_core( begin : reg_update if (!reset_n) begin - a_reg <= 64'h00000000; - b_reg <= 64'h00000000; - c_reg <= 64'h00000000; - d_reg <= 64'h00000000; - e_reg <= 64'h00000000; - f_reg <= 64'h00000000; - g_reg <= 64'h00000000; - h_reg <= 64'h00000000; - H0_reg <= 64'h00000000; - H1_reg <= 64'h00000000; - H2_reg <= 64'h00000000; - H3_reg <= 64'h00000000; - H4_reg <= 64'h00000000; - H5_reg <= 64'h00000000; - H6_reg <= 64'h00000000; - H7_reg <= 64'h00000000; - digest_valid_reg <= 0; - t_ctr_reg <= 7'h00; - sha512_ctrl_reg <= CTRL_IDLE; + a_reg <= 64'h0000000000000000; + b_reg <= 64'h0000000000000000; + c_reg <= 64'h0000000000000000; + d_reg <= 64'h0000000000000000; + e_reg <= 64'h0000000000000000; + f_reg <= 64'h0000000000000000; + g_reg <= 64'h0000000000000000; + h_reg <= 64'h0000000000000000; + H0_reg <= 64'h0000000000000000; + H1_reg <= 64'h0000000000000000; + H2_reg <= 64'h0000000000000000; + H3_reg <= 64'h0000000000000000; + H4_reg <= 64'h0000000000000000; + H5_reg <= 64'h0000000000000000; + H6_reg <= 64'h0000000000000000; + H7_reg <= 64'h0000000000000000; + work_factor_ctr_reg <= 32'h00000000; + digest_valid_reg <= 0; + t_ctr_reg <= 7'h00; + sha512_ctrl_reg <= CTRL_IDLE; end else begin @@ -257,6 +268,11 @@ module sha512_core( t_ctr_reg <= t_ctr_new; end + if (work_factor_ctr_we) + begin + work_factor_ctr_reg <= work_factor_ctr_new; + end + if (digest_valid_we) begin digest_valid_reg <= digest_valid_new; @@ -442,32 +458,65 @@ module sha512_core( //---------------------------------------------------------------- + // work_factor_ctr + // + // Work factor counter logic. + //---------------------------------------------------------------- + always @* + begin : work_factor_ctr + work_factor_ctr_new = 32'h00000000; + work_factor_ctr_we = 0; + work_factor_ctr_done = 0; + + if (work_factor_ctr_reg == work_factor_num) + begin + work_factor_ctr_done = 1; + end + + if (work_factor_ctr_rst) + begin + work_factor_ctr_new = 32'h00000000; + work_factor_ctr_we = 1; + end + + if (work_factor_ctr_inc) + begin + work_factor_ctr_new = work_factor_ctr_reg + 1'b1; + work_factor_ctr_we = 1; + end + end // work_factor_ctr + + + //---------------------------------------------------------------- // sha512_ctrl_fsm // // Logic for the state machine controlling the core behaviour. //---------------------------------------------------------------- always @* begin : sha512_ctrl_fsm - digest_init = 0; - digest_update = 0; + digest_init = 0; + digest_update = 0; - state_init = 0; - state_update = 0; + state_init = 0; + state_update = 0; - first_block = 0; - ready_flag = 0; + first_block = 0; + ready_flag = 0; - w_init = 0; - w_next = 0; + w_init = 0; + w_next = 0; - t_ctr_inc = 0; - t_ctr_rst = 0; + t_ctr_inc = 0; + t_ctr_rst = 0; - digest_valid_new = 0; - digest_valid_we = 0; + digest_valid_new = 0; + digest_valid_we = 0; - sha512_ctrl_new = CTRL_IDLE; - sha512_ctrl_we = 0; + work_factor_ctr_rst = 0; + work_factor_ctr_inc = 0; + + sha512_ctrl_new = CTRL_IDLE; + sha512_ctrl_we = 0; case (sha512_ctrl_reg) @@ -477,26 +526,28 @@ module sha512_core( if (init) begin - digest_init = 1; - w_init = 1; - state_init = 1; - first_block = 1; - t_ctr_rst = 1; - digest_valid_new = 0; - digest_valid_we = 1; - sha512_ctrl_new = CTRL_ROUNDS; - sha512_ctrl_we = 1; + work_factor_ctr_rst = 1; + digest_init = 1; + w_init = 1; + state_init = 1; + first_block = 1; + t_ctr_rst = 1; + digest_valid_new = 0; + digest_valid_we = 1; + sha512_ctrl_new = CTRL_ROUNDS; + sha512_ctrl_we = 1; end if (next) begin - w_init = 1; - state_init = 1; - t_ctr_rst = 1; - digest_valid_new = 0; - digest_valid_we = 1; - sha512_ctrl_new = CTRL_ROUNDS; - sha512_ctrl_we = 1; + work_factor_ctr_rst = 1; + w_init = 1; + state_init = 1; + t_ctr_rst = 1; + digest_valid_new = 0; + digest_valid_we = 1; + sha512_ctrl_new = CTRL_ROUNDS; + sha512_ctrl_we = 1; end end @@ -509,20 +560,42 @@ module sha512_core( if (t_ctr_reg == SHA512_ROUNDS) begin - sha512_ctrl_new = CTRL_DONE; - sha512_ctrl_we = 1; + work_factor_ctr_inc = 1; + sha512_ctrl_new = CTRL_DONE; + sha512_ctrl_we = 1; end end CTRL_DONE: begin - digest_update = 1; - digest_valid_new = 1; - digest_valid_we = 1; - - sha512_ctrl_new = CTRL_IDLE; - sha512_ctrl_we = 1; + if (work_factor) + begin + if (!work_factor_ctr_done) + begin + w_init = 1; + state_init = 1; + t_ctr_rst = 1; + sha512_ctrl_new = CTRL_ROUNDS; + sha512_ctrl_we = 1; + end + else + begin + digest_update = 1; + digest_valid_new = 1; + digest_valid_we = 1; + sha512_ctrl_new = CTRL_IDLE; + sha512_ctrl_we = 1; + end + end + else + begin + digest_update = 1; + digest_valid_new = 1; + digest_valid_we = 1; + sha512_ctrl_new = CTRL_IDLE; + sha512_ctrl_we = 1; + end end endcase // case (sha512_ctrl_reg) end // sha512_ctrl_fsm |