diff options
| -rw-r--r-- | src/rtl/sha512_core.v | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index 895c22f..b1bb496 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -282,6 +282,54 @@ module sha512_core( H7_reg <= H7_new; end + if (state00_we) + H0_reg <= {state_wr_data, H0_reg[31 : 0]}; + + if (state01_we) + H0_reg <= {H0_reg[63 : 32], state_wr_data}; + + if (state02_we) + H1_reg <= {state_wr_data, H1_reg[31 : 0]}; + + if (state03_we) + H1_reg <= {H1_reg[63 : 32], state_wr_data}; + + if (state04_we) + H2_reg <= {state_wr_data, H2_reg[31 : 0]}; + + if (state05_we) + H2_reg <= {H2_reg[63 : 32], state_wr_data}; + + if (state06_we) + H3_reg <= {state_wr_data, H3_reg[31 : 0]}; + + if (state07_we) + H3_reg <= {H3_reg[63 : 32], state_wr_data}; + + if (state08_we) + H4_reg <= {state_wr_data, H4_reg[31 : 0]}; + + if (state09_we) + H4_reg <= {H4_reg[63 : 32], state_wr_data}; + + if (state10_we) + H5_reg <= {state_wr_data, H5_reg[31 : 0]}; + + if (state11_we) + H5_reg <= {H5_reg[63 : 32], state_wr_data}; + + if (state12_we) + H6_reg <= {state_wr_data, H6_reg[31 : 0]}; + + if (state13_we) + H6_reg <= {H6_reg[63 : 32], state_wr_data}; + + if (state14_we) + H7_reg <= {state_wr_data, H7_reg[31 : 0]}; + + if (state15_we) + H7_reg <= {H7_reg[63 : 32], state_wr_data}; + if (t_ctr_we) begin t_ctr_reg <= t_ctr_new; |