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-rwxr-xr-xtoolruns/Makefile27
1 files changed, 12 insertions, 15 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile
index d6532d7..f58bb38 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -8,7 +8,7 @@
# Author: Joachim Strombergson
# Copyright (c) 2014, NORDUnet A/S
# All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
@@ -37,34 +37,28 @@
#
#===================================================================
-#WMEM_SRC=../src/rtl/sha256_w_mem.v
-#WMEM_TB_SRC=../src/tb/tb_sha256_w_mem.v
-
CORE_SRC=../src/rtl/sha512_core.v ../src/rtl/sha512_h_constants.v ../src/rtl/sha512_k_constants.v ../src/rtl/sha512_w_mem.v
CORE_TB_SRC=../src/tb/tb_sha512_core.v
TOP_SRC=../src/rtl/sha512.v
TOP_TB_SRC=../src/tb/tb_sha512.v
-#WB_SRC=../src/rtl/wb_sha256.v $(CORE_SRC)
-#WB_TB_SRC=../src/tb/tb_wb_sha256.v
-
CC=iverilog
+CC_FLAGS= -Wall
-
-all: top core
+LINT=verilator
+LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
-#wb: $(WB_TB_SRC) $(WB_SRC)
-# $(CC) -o wb.sim $(WB_TB_SRC) $(WB_SRC)
+all: top core
-top: $(TOP_TB_SRC) $(TOP_SRC)
- $(CC) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC)
+top: $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC)
+ $(CC) $(CC_FLAGS) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC)
core: $(CORE_TB_SRC) $(CORE_SRC)
- $(CC) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
+ $(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
sim-top: top.sim
@@ -75,6 +69,10 @@ sim-core: core.sim
./core.sim
+lint: $(TOP_SRC) $(CORE_SRC)
+ $(LINT) $(LINT_FLAGS) $(TOP_SRC) $(CORE_SRC)
+
+
clean:
rm -f top.sim
rm -f core.sim
@@ -94,4 +92,3 @@ help:
#===================================================================
# EOF Makefile
#===================================================================
-